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PDF ( 数据手册 , 数据表 ) ADC0803

零件编号 ADC0803
描述 8-Bit/ Microprocessor-Compatible/ A/D Converters
制造商 Intersil Corporation
LOGO Intersil Corporation LOGO 


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ADC0803 数据手册, 描述, 功能
®
Data Sheet
ADC0803, ADC0804
August 2002
FN3094.4
8-Bit, Microprocessor-Compatible, A/D
Converters
The ADC080X family are CMOS 8-Bit, successive-
approximation A/D converters which use a modified
potentiometric ladder and are designed to operate with the
8080A control bus via three-state outputs. These converters
appear to the processor as memory locations or I/O ports,
and hence no interfacing logic is required.
The differential analog voltage input has good common-
mode-rejection and permits offsetting the analog zero-input-
voltage value. In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
Typical Application Schematic
ANY
µPROCESSOR
1 CS
2 RD
V+ 20 +5V 150pF
CLK R 19
3 WR CLK IN 4 10K
5 INTR
11 DB7
12 DB6
13 DB5
14 DB4
15 DB3
16 DB2
17 DB1
18 DB0
VIN (+)
VIN (-)
AGND
6
7
8
DIFF
INPUTS
VREF/2 9 VREF/2
DGND 10
8-BIT RESOLUTION
OVER ANY
DESIRED
ANALOG INPUT
VOLTAGE RANGE
Features
• 80C48 and 80C80/85 Bus Compatible - No Interfacing
Logic Required
• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . <100µs
• Easy Interface to Most Microprocessors
• Will Operate in a “Stand Alone” Mode
• Differential Analog Voltage Inputs
• Works with Bandgap Voltage References
• TTL Compatible Inputs and Outputs
• On-Chip Clock Generator
• Analog Voltage Input Range
(Single + 5V Supply) . . . . . . . . . . . . . . . . . . . . . . 0V to 5V
• No Zero-Adjust Required
• 80C48 and 80C80/85 Bus Compatible - No Interfacing
Logic Required
Pinout
ADC0803, ADC0804
(PDIP)
TOP VIEW
CS 1
RD 2
WR 3
CLK IN 4
INTR 5
VIN (+) 6
VIN (-) 7
AGND 8
VREF/2 9
DGND 10
20 V+ OR VREF
19 CLK R
18 DB0 (LSB)
17 DB1
16 DB2
15 DB3
14 DB4
13 DB5
12 DB6
11 DB7 (MSB)
Ordering Information
PART NUMBER
ADC0803LCN
ADC0804LCN
ERROR
±1/2 LSB
±1 LSB
EXTERNAL CONDITIONS
VREF/2 Adjusted for Correct Full Scale
Reading
VREF/2 = 2.500VDC (No Adjustments)
TEMP. RANGE (oC)
PACKAGE
0 to 70
20 Ld PDIP
0 to 70
20 Ld PDIP
PKG. NO
E20.3
E20.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved







ADC0803 pdf, 数据表
ADC0803, ADC0804
Understanding A/D Error Specs
A perfect A/D transfer characteristic (staircase wave-form) is
shown in Figure 11A. The horizontal scale is analog input
voltage and the particular points labeled are in steps of 1
LSB (19.53mV with 2.5V tied to the VREF/2 pin). The digital
output codes which correspond to these inputs are shown as
D-1, D, and D+1. For the perfect A/D, not only will center-
value (A - 1, A, A + 1, . . .) analog inputs produce the correct
output digital codes, but also each riser (the transitions
between adjacent output codes) will be located ±1/2 LSB
away from each center-value. As shown, the risers are ideal
and have no width. Correct digital output codes will be
provided for a range of analog input voltages which extend
±1/2 LSB from the ideal center-values. Each tread (the range
of analog input voltage which provides the same digital
output code) is therefore 1 LSB wide.
The error curve of Figure 11B shows the worst case transfer
function for the ADC080X. Here the specification guarantees
that if we apply an analog input equal to the LSB analog
voltage center-value, the A/D will produce the correct digital
code.
Next to each transfer function is shown the corresponding
error plot. Notice that the error includes the quantization
uncertainty of the A/D. For example, the error at point 1 of
F1/i2guLrSeB11inAaisdv+a1n/2ceLSofBthbeeccaeunsteer-tvhaeludeigoitaf lthceodtreeaadp.pTehaered
error plots always have a constant negative slope and the
abrupt upside steps are always 1 LSB in magnitude, unless
the device has missing codes.
Detailed Description
The functional diagram of the ADC080X series of A/D
converters operates on the successive approximation
principle (see Application Notes AN016 and AN020 for a
more detailed description of this principle). Analog switches
are closed sequentially by successive-approximation logic
until the analog differential input voltage [VlN(+) - VlN(-)]
matches a voltage derived from a tapped resistor string
across the reference voltage. The most significant bit is
tested first and after 8 comparisons (64 clock cycles), an 8-
bit binary code (1111 1111 = full scale) is transferred to an
output latch.
The normal operation proceeds as follows. On the high-to-low
transition of the WR input, the internal SAR latches and the
shift-register stages are reset, and the INTR output will be set
high. As long as the CS input and WR input remain low, the
A/D will remain in a reset state. Conversion will start from 1 to
8 clock periods after at least one of these inputs makes a low-
to-high transition. After the requisite number of clock pulses to
complete the conversion, the INTR pin will make a high-to-low
transition. This can be used to interrupt a processor, or
otherwise signal the availability of a new conversion. A RD
operation (with CS low) will clear the INTR line high again.
The device may be operated in the free-running mode by
connecting INTR to the WR input with CS = 0. To ensure start-
up under all possible conditions, an external WR pulse is
required during the first power-up cycle. A conversion-in-
process can be interrupted by issuing a second start
command.
Digital Operation
The converter is started by having CS and WR simultaneously
low. This sets the start flip-flop (F/F) and the resulting “1” level
resets the 8-bit shift register, resets the Interrupt (INTR) F/F
and inputs a “1” to the D flip-flop, DFF1, which is at the input
end of the 8-bit shift register. Internal clock signals then
transfer this “1” to the Q output of DFF1. The AND gate, G1,
combines this “1” output with a clock signal to provide a reset
signal to the start F/F. If the set signal is no longer present
(either WR or CS is a “1”), the start F/F is reset and the 8-bit
shift register then can have the “1” clocked in, which starts the
conversion process. If the set signal were to still be present,
this reset pulse would have no effect (both outputs of the start
F/F would be at a “1” level) and the 8-bit shift register would
continue to be held in the reset mode. This allows for
asynchronous or wide CS and WR signals.
After the “1” is clocked through the 8-bit shift register (which
completes the SAR operation) it appears as the input to
DFF2. As soon as this “1” is output from the shift register, the
AND gate, G2, causes the new digital word to transfer to the
Three-State output latches. When DFF2 is subsequently
clocked, the Q output makes a high-to-low transition which
causes the INTR F/F to set. An inverting buffer then supplies
the INTR output signal.
When data is to be read, the combination of both CS and RD
being low will cause the INTR F/F to be reset and the three-
state output latches will be enabled to provide the 8-bit
digital outputs.
Digital Control Inputs
The digital control inputs (CS, RD, and WR) meet standard
TTL logic voltage levels. These signals are essentially
equivalent to the standard A/D Start and Output Enable
control signals, and are active low to allow an easy interface
to microprocessor control busses. For non-microprocessor
based applications, the CS input (pin 1) can be grounded and
the standard A/D Start function obtained by an active low
pulse at the WR input (pin 3). The Output Enable function is
achieved by an active low pulse at the RD input (pin 2).
Analog Operation
The analog comparisons are performed by a capacitive
charge summing circuit. Three capacitors (with precise ratioed
values) share a common node with the input to an auto-
zeroed comparator. The input capacitor is switched between
VlN(+) and VlN(-), while two ratioed reference capacitors are
switched between taps on the reference voltage divider string.
The net charge corresponds to the weighted difference
between the input and the current total value set by the
8







ADC0803 equivalent, schematic
ADC0803, ADC0804
Die Characteristics
DIE DIMENSIONS
101 mils x 93 mils
METALLIZATION
Type: Al
Thickness: 10kÅ ±1kÅ
Metallization Mask Layout
PASSIVATION
Type: Nitride over Silox
Nitride Thickness: 8kÅ
Silox Thickness: 7kÅ
ADC0803, ADC0804
AGND
VIN (-)
VIN (+)
INTR
CLK IN
WR
VREF/2
DGND
DB7 (MSB)
DB6
DB5
DB4
DB3
DB2
DB1
DB0
RD
CS
V+ OR VREF
V+ OR VREF
CLK R
16










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