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零件编号 | A627308X-70S | ||
描述 | 128K X 8 BIT CMOS SRAM | ||
制造商 | AMIC Technology | ||
LOGO | |||
1 Page
Preliminary
Document Title
128K X 8 BIT CMOS SRAM
Revision History
Rev. No. History
0.0 Initial issue
A627308 Series
128K X 8 BIT CMOS SRAM
Issue Date
August 15, 2000
Remark
Preliminary
PRELIMINARY (August, 2000, Version 0.0)
AMIC Technology, Inc.
Timing Waveforms (continued)
Read Cycle 3 (1, 3, 4, 6)
A627308 Series
CE1
DOUT
Read Cycle 4 (1, 4, 7, 8)
CE2
DOUT
tCLZ15
tACE1
tCLZ25
tACE2
tCHZ15
tCHZ25
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high.
7. CE1 is low.
8. Address valid prior to or coincident with CE2 transition high.
PRELIMINARY
(August, 2000, Version 0.0)
7
AMIC Technology, Inc.
Package Information
sTSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions
A627308 Series
unit: inches/mm
0.076MM
SEATING PLANE
θ
L
D1 LE
D
Detail "A"
Detail "A"
Sb
Symbol
A
A1
A2
b
c
E
e
D
D1
L
LE
S
θ
Dimensions in inches
Min Nom Max
- - 0.049
0.002
-
-
0.037 0.039 0.041
0.007 0.008 0.009
0.0056 0.0059 0.0062
0.311 0.315 0.319
0.020 TYP
0.520 0.528 0.535
0.461 0.465 0.469
0.012 0.020 0.028
0.0275 0.0315 0.0355
0.0109 TYP
0° 3° 5°
Dimensions in mm
Min Nom Max
- - 1.25
0.05 -
-
0.95 1.00 1.05
0.17 0.20 0.23
0.142 0.150 0.158
7.90 8.00 8.10
0.50 TYP
13.20 13.40 13.60
11.70 11.80 11.90
0.30 0.50 0.70
0.700 0.800 0.900
0.278 TYP
0° 3° 5°
Notes:
1. The maximum value of dimension D1 includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
PRELIMINARY
(August, 2000, Version 0.0)
15
AMIC Technology, Inc.
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页数 | 16 页 | ||
下载 | [ A627308X-70S.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
A627308X-70S | 128K X 8 BIT CMOS SRAM | AMIC Technology |
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