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零件编号 | A616316 | ||
描述 | 64K X 16 BIT HIGH SPEED CMOS SRAM | ||
制造商 | AMIC Technology | ||
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1 Page
A615308 Series
Preliminary
32K X 8 BIT HIGH SPEED CMOS SRAM
Document Title
32K X 8 BIT HIGH SPEED CMOS SRAM
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
January 17, 2001
Remark
PRELIMINARY (January, 2001, Version 0.0)
AMIC Technology, Inc.
A615308 Series
Timing Waveforms (continued)
Write Cycle 1(6)
(Write Enable Controlled)
Address
CE (4)
tAS1
WE
DIN
DOUT
tWC
tAW
tCW 5
tWP2
tWR 3
tWHZ7
tDW
tDH
tOW 7
Write Cycle 2
(Chip Enable Controlled)
Address
CE
tWC
tAS1
(4)
tAW
tCW5
tWR3
WE
DIN
DOUT
tWP2
tDW
tWHZ7
tDH
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE and a low WE .
3. tWR is measured from the earliest of CE or WE going high to the end of the Write cycle
4. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs
remain in a high impedance state.
5. tCW is measured from the later of CE going low to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (January, 2001, Version 0.0)
7
AMIC Technology, Inc.
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页数 | 12 页 | ||
下载 | [ A616316.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
A616316 | 64K X 16 BIT HIGH SPEED CMOS SRAM | AMIC Technology |
A616316S | 64K X 16 BIT HIGH SPEED CMOS SRAM | AMIC Technology |
A616316S-12 | 64K X 16 BIT HIGH SPEED CMOS SRAM | AMIC Technology |
A616316S-15 | 64K X 16 BIT HIGH SPEED CMOS SRAM | AMIC Technology |
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