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PDF ( 数据手册 , 数据表 ) A80960HD66SL2GJ

零件编号 A80960HD66SL2GJ
描述 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor
制造商 Intel Corporation
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A80960HD66SL2GJ 数据手册, 描述, 功能
80960HA/HD/HT 32-Bit High-Performance
Superscalar Processor
Data Sheet
Advance Information
Product Features
s 32-Bit Parallel Architecture
—Load/Store Architecture
—Sixteen 32-Bit Global Registers
—Sixteen 32-Bit Local Registers
—1.28 Gbyte Internal Bandwidth
(80 MHz)
—On-Chip Register Cache
s Processor Core Clock
—80960HA is 1x Bus Clock
—80960HD is 2x Bus Clock
—80960HT is 3x Bus Clock
s Binary Compatible with Other 80960
Processors
s Issue Up To 150 Million Instructions per
Second
s High-Performance On-Chip Storage
—16 Kbyte Four-Way Set-Associative
Instruction Cache
—8 Kbyte Four-Way Set-Associative Data
Cache
—2 Kbyte General Purpose RAM
—Separate 128-Bit Internal Paths For
Instructions/Data
s 3.3 V Supply Voltage
—5 V Tolerant Inputs
—TTL Compatible Outputs
s Guarded Memory Unit
—Provides Memory Protection
—User/Supervisor Read/Write/Execute
s 32-Bit Demultiplexed Burst Bus
—Per-Byte Parity Generation/Checking
—Address Pipelining Option
—Fully Programmable Wait State
Generator
—Supports 8-, 16- or 32-Bit Bus Widths
—160 Mbyte/s External Bandwidth
(40 MHz)
s High-Speed Interrupt Controller
—Up to 240 External Interrupts
—31 Fully Programmable Priorities
—Separate, Non-maskable Interrupt Pin
s Dual On-Chip 32-Bit Timers
—Auto Reload Capability and One-Shot
—CLKIN Prescaling, ÷1, 2, 4 or 8
—JTAG Support - IEEE 1149.1 Compliant
Notice: This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify with your
local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 272495-007
July, 1998







A80960HD66SL2GJ pdf, 数据表
80960HA/HD/HT
2.1
2.2
2.2.1
2.2.2
2
In addition to expanded clock frequency options, the 80960Hx provides essential enhancements for
an emerging class of high-performance embedded applications. Features include a larger
instruction cache, data cache, and data RAM than any other 80960 processor to date. It also boasts
a 32-bit demultiplexed and pipelined burst bus, fast interrupt mechanism, guarded memory unit,
wait state generator, dual programmable timers, ONCE and IEEE 1149.1-compliant boundary scan
test and debug support, and new instructions.
The i960® Processor Family
The i960 processor family is a 32-bit RISC architecture created by Intel to serve the needs of
embedded applications. The embedded market includes applications as diverse as industrial
automation, avionics, image processing, graphics and communications.
Because all members of the i960 processor family share a common core architecture, i960
applications are code-compatible. Each new processor in the family adds its own special set of
functions to the core to satisfy the needs of a specific application or range of applications in the
embedded market.
Key 80960Hx Features
Execution Architecture
Independent instruction paths inside the processor allow the execution of multiple, out-of-sequence
instructions per clock. Register and resource scoreboarding interlocks maintain the logical integrity
of sequential instructions that are being executed in parallel. To sustain execution of multiple
instructions in each clock cycle, the processor decodes multiple instructions in parallel and
simultaneously issues these instructions to parallel processing units. The various processing units
are then able to independently access instruction operands in parallel from a common register set.
Local Register Cache integrated on-chip provides automatic register management on call/return
instructions. Upon a call instruction, the processor allocates a set of local registers for the called
procedure, then stores the registers for the previous procedure in the on-chip register cache. As
additional procedures are called, the cache stores the associated registers such that the most recently
called procedure is the first available by the next return (ret) instruction. The processor can store up to
fifteen register sets, after which the oldest sets are stored (spilled) into external memory.
The 80960Hx supports the 80960 architecturally-defined branch prediction mechanism. This
allows many branches to execute with no pipeline break. With the 80960Hx’s efficient pipeline, a
branch can take as few as zero clocks to execute. The maximum penalty for an incorrect prediction
is two core clocks.
Pipelined, Burst Bus
A 32-bit high performance bus controller interfaces the 80960Hx core to the external memory and
peripherals. The Bus Control Unit features a maximum transfer rate of 160 Mbytes per second (at a
40 MHz external bus clock frequency). A key advantage of this design is its versatility. The user
can independently program the physical and logical attributes of system memory. Physical
attributes include wait state profile, bus width, and parity. Logical attributes include cacheability
and Big or Little Endian byte order. Internally programmable wait states and 16 separately
configurable physical memory regions allow the processor to interface with a variety of memory
Advance Information Datasheet







A80960HD66SL2GJ equivalent, schematic
80960HA/HD/HT
Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 3 of 4)
Name
Type
Description
HOLD
HOLDA
BOFF
BREQ
BSTALL
CT3:0
XINT7:0
NMI
I
S(L)
O
H(1)
B(0)
R(Q)
I
S(L)
O
H(Q)
B(Q)
R(0)
O
H(Q)
B(Q)
R(0)
O
H(Z)
B(Z)
R(Z)
I
A(E)
A(L)
I
A(E)
HOLD REQUEST signals that an external agent requests access to the
processor’s address, data, and control buses. When HOLD is asserted, the
processor:
Completes the current bus request.
Asserts HOLDA and floats the address, data, and control buses.
When HOLD is deasserted, the HOLDA pin is deasserted and the processor
reassumes control of the address, data, and control pins.
HOLD ACKNOWLEDGE indicates to an external master that the processor has
relinquished control of the bus. The processor grants HOLD requests and enters
the HOLDA state while the RESET pin is asserted.
HOLDA is never granted while LOCK is asserted.
BUS BACKOFF forces the processor to immediately relinquish control of the bus
on the next clock cycle. When READY/BTERM is enabled and:
When BOFF is asserted, the address, data, and control buses are floated on the
next clock cycle and the current access is aborted.
When BOFF is deasserted, the processor resumes by regenerating the aborted
bus access.
See Figure 16 on page 40 for BOFF timing requirements.
BUS REQUEST indicates that a bus request is pending in the bus controller.
BREQ does not indicate whether or not the processor is stalled. See BSTALL for
processor stall status. BREQ can be used with BSTALL to indicate to an external
bus arbiter the processor’s bus ownership requirements.
BUS STALL indicates that the processor has stalled pending the result of a
request in the bus controller. When BSTALL is asserted, the processor must
regain bus ownership to continue processing (i.e., it can no longer execute strictly
out of on-chip cache memory).
CYCLE TYPE indicates the type of bus cycle currently being started or processor
state. CT3:0 encoding follows:
Cycle Type
ADSCT3:0
Program-initiated access using 8-bit bus
Program-initiated access using 16-bit bus
Program-initiated access using 32-bit bus
Event-initiated access using 8-bit bus
Event-initiated access using 16-bit bus
Event-initiated access using 32-bit bus
Reserved
Reserved for future products
Reserved
00000
00001
00010
00100
00101
00110
00X11
01XXX
1XXXX
EXTERNAL INTERRUPT pins are used to request interrupt service. These pins
can be configured in three modes:
Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated
inputs can be programmed to be level (low or high) or edge (rising or falling)
sensitive.
Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt
pins are level sensitive in this mode.
Mixed Mode: The XINT7:5 pins act as dedicated sources and the XINT4:0 pins act
as the five most significant bits of a vectored source. The least significant bits of
the vectored source are set to “010” internally.
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI is the highest priority interrupt source. NMI is falling edge triggered.
10 Advance Information Datasheet










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