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PDF ( 数据手册 , 数据表 ) AD28MSP02

零件编号 AD28MSP02
描述 Voiceband Signal Port
制造商 Analog Devices
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AD28MSP02 数据手册, 描述, 功能
a
FEATURES
Complete Analog I/O Port for Voiceband DSP
Applications
Linear-Coded 16-Bit Sigma-Delta ADC
Linear-Coded 16-Bit Sigma-Delta DAC
On-Chip Anti-Aliasing and Anti-lmaging Filters
On-Chip Voltage Reference
8 kHz Sampling Frequency
Twos Complement Coding
65 dB SNR + THD
Programmable Gain on DAC and ADC
Serial Interface To DSP Processors
24-Pin DlP/28-Lead SOIC
Single 5 V Power Supply
Voiceband Signal Port
AD28msp02
FUNCTIONAL BLOCK DIAGRAM
VOICEBAND
ANALOG
INPUT A
VOICEBAND
ANALOG
INPUT B
MUX
+20dB
AMP
VOLTAGE
REFERENCE
16-BIT
SIGMA-
DELTA ADC
DIGITAL
DATA AND
CONTROL
SERIAL
PORT
DIFFERENTIAL
ANALOG
OUTPUT
PGA
16-BIT
SIGMA-
DELTA DAC
GENERAL DESCRIPTION
The AD28msp02 Voiceband Signal Port is a complete analog
front end for high performance voiceband DSP applications.
Compared to traditional µ-law and A-law codecs, the
AD28msp02’s linear-coded ADC and DAC maintain wide
dynamic range while maintaining superior SNR and THD. A
sampling rate of 8.0 kHz coupled with 65 dB SNR + THD per-
formance make the AD28msp02 attractive in many telecom and
speech processing applications, for example digital cellular radio
and high quality telephones. The AD28msp02 simplifies overall
system design by requiring only a single +5 V power supply.
The inclusion of on-chip anti-aliasing and anti-imaging filters,
16-bit sigma-delta ADC and DAC, and programmable gain
amplifiers ensures a highly integrated and compact solution to
voiceband analog processing requirements. Sigma-delta conver-
sion technology eliminates the need for complex off-chip anti-
aliasing filters and sample-and-hold circuitry.
The AD28msp02’s serial I/O port provides an easy interface to
host DSP microprocessors such as the ADSP-2101, ADSP-2105
and ADSP-2111. The AD28msp02 is available in a 24-pin, 0.3"
plastic DIP and a 28-lead SOIC package.
FUNCTIONAL DESCRIPTION
Figure 1 shows a block diagram of the AD28msp02.
A/D CONVERSION
The A/D conversion circuitry of the AD28msp02 consists of two
analog input amplifiers, an optional 20 dB preamplifier, and
a sigma-delta analog-to-digital converter (ADC). The analog
input signal to the AD28msp02 must be ac-coupled.
Analog Input Amplifiers
The two analog input amplifiers (NORM, AUX) are internally
biased by an on-chip voltage reference in order to allow opera-
tion of the AD28msp02 with a single +5 V power supply.
An analog multiplexer selects either the NORM or AUX ampli-
fier as the input to the ADC’s sigma-delta modulator. The
optional 20 dB preamplifier may be used to increase the signal
level; the preamplifier can be inserted before the modulator or
can be bypassed. Input signal level to the sigma-delta modulator
should not exceed VINMAX, which is specified under “Analog
Interface Electrical Characteristics.” Refer to “Analog Input” in
the “Design Considerations” section of this data sheet for more
information.
The input multiplexer and 20 dB preamplifier are configured by
Bits 0 and 1 (IPS, IMS) of the AD28msp02’s control register. If
the multiplexer setting is changed while an input signal is being
processed, the ADC’s output must be allowed time to settle to
ensure that the output data is valid.
ADC
The ADC consists of a 2nd-order analog sigma-delta modulator,
an anti-aliasing decimation filter, and a digital high-pass filter.
The sigma-delta modulator noise-shapes the signal and pro-
duces 1-bit samples at a 1.0 MHz rate. This bit stream, which
represents the analog input signal, is fed to the anti-aliasing
decimation filter.
Decimation Filter
The anti-aliasing decimation filter contains two stages. The first
stage is a sinc4 digital filter that increases resolution to 16 bits
and reduces the sample rate to 40 kHz. The second stage is an
IIR low-pass filter.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703







AD28MSP02 pdf, 数据表
AD28msp02
To select values for the components shown in Figure 7, use the
following equations:
Gain = RFB
RIN
CI N
=
1
60 π RIN
CFB
=
1
(2 π)(20 × 103 ) RFB
10 kΩ ≤ RFB, RIN 50 k
150 pF CFB 600 pF
Figure 8 shows an example of a typical input circuit configured
for 0 dB gain. The circuit’s diodes are used to prevent the input
signal from exceeding maximum limits.
VCC
330pF
INPUT
10k
SIGNAL
1.0µF
10k
20k
VFBNORM
VINNORM
GNDA
VFBAUX
VINAUX
MUX
VOLTAGE
REFERENCE
AD28msp02
Figure 8. Example Analog Input Circuit for 0 dB Gain
Analog Output
The AD28msp02’s differential analog output (VOUTP, VOUTN)
is produced by an on-chip differential amplifier. The differential
amplifier can drive a minimum load of 2 k(RL 2 k) and
has a maximum differential output voltage swing of ± 3.156 V
peak-to-peak (3.17 dBm0). The differential output can be
ac-coupled directly to a load or dc-coupled to an external
amplifier.
Figure 9 shows a simple circuit providing a differential output
with ac coupling. The capacitor of this circuit (COUT) is
optional; if used, its value can be chosen as follows:
COUT
=1
(60 π) RL
AD28msp02
C OUT
VOUTP
RL
C OUT
VOUT N
Figure 9. Example Circuit for Differential Output
The VOUTP–VOUTN outputs must be used as differential out-
puts; do not use either as a single-ended output. Figure 10
shows an example circuit which can be used to convert the dif-
ferential output to a single-ended output. The circuit uses a
differential-to-single-ended amplifier, the Analog Devices
SSM2141.
+12 V
AD28msp02
0.1 µF
GNDA
VOUT
7
5
SSM2141
1
4
VOUTP
VOUTN
GNDA
–12 V
0.1 µF
GNDA
Figure 10. Example Circuit for Single-Ended Output
–8– REV. 0







AD28MSP02 equivalent, schematic
AD28msp02
NOISE AND DISTORTION
Parameter
ADC Intermodulation Distortion
DAC Intermodulation Distortion
ADC Idle Channel Noise
DAC Idle Channel Noise
ADC Crosstalk
DAC Crosstalk
ADC Power Supply Rejection
DAC Power Supply Rejection
ADC Group Delay1
DAC Group Delay1
1Guaranteed but not tested.
Min
70
Max
–70
–70
72
72
–65
–65
–55
55
1
1
Unit
dB
dB
dBm0
dBm0
dB
dB
dB
dB
ms
ms
Test Conditions
ADC input signal level: 1.0 kHz, 0 dBm0
DAC input at idle
ADC input signal level: analog ground
DAC output signal level: 1.0 kHz, 0 dBm0
Input signal level at VCC and VDD pins:
1.0 kHz, 100 mV p-p sine wave
Input signal level at VCC and VDD pins:
1.0 kHz, 100 mV p-p sine wave
300–3000 Hz
300–3000 Hz
60
50
40
30
20
10
0
–10
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
VIN – dBm0
0
3.17
Figure 17. SNR + THD vs. VIN
ORDERING GUIDE
Part
Number
Temperature
Range
Package
Package
Option*
AD28msp02KN
AD28msp02KR
AD28msp02BN
AD28msp02BR
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
*N = Plastic DIP, R = Small Outline (SOIC).
24-Pin Plastic DIP
28-Lead SOIC
24-Pin Plastic DIP
28-Lead SOIC
N-24
R-28
N-24
R-28
–16–
REV. 0










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