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PDF ( 数据手册 , 数据表 ) AD5260

零件编号 AD5260
描述 8-Bit Dual Nonvolatile Memory Digital Potentiometer
制造商 Analog Devices
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AD5260 数据手册, 描述, 功能
a
1-/2-Channel
15 V Digital Potentiometers
AD5260/AD5262
FEATURES
256 Positions
AD5260 – 1-Channel
AD5262 – 2-Channel (Independently Programmable)
Potentiometer Replacement
20 k, 50 k, 200 k
Low Temperature Coefficient 35 ppm/؇C
4-Wire SPI-Compatible Serial Data Input
5 V to 15 V Single-Supply; ؎5.5 V Dual-Supply Operation
Power ON Mid-Scale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Stereo Channel Audio Level Control
Programmable Voltage to Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Low Resolution DAC Replacement
GENERAL DESCRIPTION
The AD5260/AD5262 provide a single- or dual-channel, 256-
position, digitally controlled variable resistor (VR) device.* These
devices perform the same electronic adjustment function as a
potentiometer or variable resistor. Each channel of the AD5260/
AD5262 contains a fixed resistor with a wiper contact that taps the
fixed resistor value at a point determined by a digital code loaded
into the SPI-compatible serial-input register. The resistance between
the wiper and either end point of the fixed resistor varies linearly
with respect to the digital code transferred into the VR latch. The
variable resistor offers a completely programmable value of resistance,
between the A terminal and the wiper or the B terminal and the wiper.
The fixed A to B terminal resistance of 20 kW, 50 kW, or 200 kW has
a nominal temperature coefficient of 35 ppm/C. Unlike the majority
of the digital potentiometers in the market, these devices can operate
up to 15 V or ±5 V provided proper supply voltages are furnished.
Each VR has its own VR latch, which holds its programmed resistance
value. These VR latches are updated from an internal serial-to-parallel
shift register, which is loaded from a standard 3-wire serial-input
digital interface. The AD5260 contains an 8-bit serial register
while the AD5262 contains a 9-bit serial register. Each bit is clocked
into the register on the positive edge of the CLK. The AD5262
address bit determines the corresponding VR latch to be loaded
with the last 8 bits of the data word during the positive edging of
CS strobe. A serial data output pin at the opposite end of the serial
register enables simple daisy chaining in multiple VR applications
without additional external decoding logic. An optional reset pin
(PR) forces the wiper to the mid-scale position by loading 80H into
the VR latch.
*The terms digital potentiometers, VR, and RDAC are used interchangeably.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAMS
A WB
SHDN
VDD
VSS
VL
CS
CLK
SDI
GND
RDAC
REGISTER
AD5260
LOGIC
POWER-ON
RESET
8
SERIAL INPUT REGISTER
PR
SDO
A1 W1 B1
A2 W2 B2
SHDN
VDD
VSS
VL
CS
CLK
SDI
GND
RDAC1 REGISTER
RDAC2 REGISTER
LOGIC
POWER-ON
RESET
8
SERIAL INPUT REGISTER
AD5262
PR
SDO
100
RWA
75
RWB
50
25
0
0 64 128 192 256
CODE – Decimal
Figure 1. RWA and RWB vs. Code
The AD5260/AD5262 are available in thin surface-mount TSSOP-14
and TSSOP-16 packages. All parts are guaranteed to operate over
the extended industrial temperature range of –40C to +85C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002







AD5260 pdf, 数据表
AD5260/AD5262
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure as shown in Figure 6. This applies
to digital input pins CS, SDI, SDO, PR, SHDN, and CLK.
340
LOGIC
Figure 6. ESD Protection of Digital Pins
A, B, W
VSS
Figure 7. ESD Protection of Resistor Terminals
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum-lead length
layout design. The leads to the input should be as direct as pos-
sible with a minimum conductor length. Ground paths should
have low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 mF–0.1 mF disc or chip ceram-
ics capacitors. Low-ESR 1 mF to 10 mF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize any
transient disturbance (see Figure 8). Notice the digital ground
should also be joined remotely to the analog ground to minimize
the ground bounce.
VDD
؉
C3 C1
10F 0.1F
؉
C4 C2
VSS 10F 0.1F
VDD
VSS GND
Figure 8. Power Supply Bypassing
TERMINAL VOLTAGE OPERATING RANGE
The AD5260/AD5262 positive VDD and negative VSS power
supply defines the boundary conditions for proper 3-terminal
digital potentiometer operation. Supply signals present on termi-
nals A, B, and W that exceed VDD or VSS will be clamped by the
internal forward biased diodes (see Figure 9).
VDD
A
W
B
VSS
Figure 9. Maximum Terminal Voltages Set by VDD and VSS
The ground pin of the AD5260/AD5262 device is primarily used
as a digital ground reference, which needs to be tied to the PCB’s
common ground. The digital input control signals to the AD5260/
AD5262 must be referenced to the device ground pin (GND),
and must satisfy the logic level defined in the specification table
of this data sheet. An internal level shift circuit ensures that the
common-mode voltage range of the three terminals extends
from VSS to VDD regardless of the digital input level.
POWER-UP SEQUENCE
Since there are diodes to limit the voltage compliance at termi-
nals A, B, and W (see Figure 9), it is important to power VDD/VSS
first before applying any voltage to terminals A, B, and W. Other-
wise, the diode will be forward biased such that VDD/VSS will be
powered unintentionally and may affect the rest of the user’s circuit.
The ideal power-up sequence is in the following order: GND,
VDD, VSS, VL, Digital Inputs, and VA/B/W. The order of powering
VA, VB, VW, and Digital Inputs is not important as long as they
are powered after VDD/VSS.
Daisy-Chain Operation
The serial-data output (SDO) pin contains an open drain
n-channel FET. This output requires a pull-up resistor to trans-
fer data to the next package’s SDI pin. This allows for daisy
chaining several RDACs from a single processor serial data line.
The pull-up resistor termination voltage can be larger than the VDD
supply voltage. It is recommended to increase the Clock period
when using a pull-up resistor to the SDI pin of the following device
in series because capacitive loading at the daisy-chain node
SDO-SDI between devices may induce time delay to subsequent
devices. Users should be aware of this potential problem to achieve
data transfer successfully (see Figure 10). If two AD5260s are daisy-
chained, this requires a total of 16 bits of data. The first 8 bits,
complying with the format shown in Table I, go to U2, and the
second 8 bits with the same format go to U1. The CS should be
kept low until all 16 bits are clocked into their respective serial
registers, and the CS is then pulled high to complete the operation.
VDD
C MOSI
SCLK SS
AD5260
U1
SDI SDO
CS CLK
RP
2.2k
AD5260
U2
SDI SDO
CS CLK
Figure 10. Daisy-Chain Configuration
RDAC STRUCTURE
The RDAC contains a string of equal resistor segments, with an
array of analog switches, that act as the wiper connection. The
number of positions is the resolution of the device. The AD5260/
AD5262 have 256 connection points allowing it to provide better
than 0.4% set-ability resolution. Figure 11 shows an equivalent
structure of the connections between the three terminals that
make up one channel of the RDAC. The SWA and SWB will
always be ON, while one of the switches SW(0) to SW(2N – 1)
will be ON one at a time depending on the resistance position
decoded from the data bits. Since the switch is not ideal, there is
a 60 W wiper resistance, RW. Wiper resistance is a function of
supply voltage and temperature. The lower the supply voltage, the
higher the wiper resistance. Similarly, the higher the temperature,
the higher the wiper resistance. Users should be aware of the
contribution of the wiper resistance when accurate prediction of
the output resistance is needed.
–8– REV. 0







AD5260 equivalent, schematic
AD5260/AD5262
that can deliver 20 mA at 2.048 V. The load current is simply the
voltage across terminals B-to-W of the digital pot divided by RS.
IL
=
VREF ¥
RS
D
(7)
؉5V
2 U1
VIN
REF191
3 SLEEP
6
VOUT
0 TO (2.048 ؉ VL)
GND
C1
1F
AD5260
4
BW
A
+5V
–2.048V TO VL
U2
OP1177
+
–5V
RS
102
RL
100
VL
IL
Figure 19. Programmable 4-to-20 mA Current Source
The circuit is simple, but be aware that dual-supply op amps are
ideal because the ground potential of REF191 can swing from
–2.048 V at zero scale to VL at full scale of the potentiometer
setting. Although the circuit works under single supply, the pro-
grammable resolution of the system will be reduced.
Programmable Bidirectional Current Source
For applications that require bidirectional current control or higher
voltage compliance, a Howland current pump can be a solution
(see Figure 20). If the resistors are matched, the load current is:
( )IL =
R2A + R2B
R2B
/R1
¥ VW
(8)
R1
150k
R2
15k
C1
10pF
+15V
+5V
A
AD5260
W
B
–5V
+15V
OP2177
A1
–15V
C2
10pF
R1
150k
A2
AD8016
–15V
RL
50
R2A
14.95k
RL
500
VL
IL
Figure 20. Programmable Bidirectional Current Source
Programmable Low-Pass Filter
Digital potentiometer AD5262 can be used to construct a second
order Sallen Key Low-Pass Filter (see Figure 21). The design
equations are:
VO
Vi
=
wO2
S2
+
wO
Q
S
+
wO2
(9)
1
wO = R1R2C1C2
(10)
Q
=
1
R1C1
+
1
R2C2
(11)
Users can first select some convenient values for the capacitors.
To achieve maximally flat bandwidth where Q = 0.707, let C1 be
twice the size of C2 and let R1 = R2. As a result, users can adjust
R1 and R2 to the same settings to achieve the desirable bandwidth.
C1
R1 R2
Vi A B A B
W
R
W
R
+2.5V
AD8601
VO
C2 –2.5V
ADJUSTED TO
SAME SETTINGS
Figure 21. Sallen Key Low-Pass Filter
Programmable Oscillator
In a classic Wien-bridge oscillator, Figure 22, the Wien network
(R, R, C, C) provides positive feedback, while R1 and R2
provide negative feedback. At the resonant frequency, fo, the
overall phase shift is zero, and the positive feedback causes the
circuit to oscillate. With R = R, C = C, and R2 = R2A//(R2B+
RDIODE), the oscillation frequency is:
wO
=
1
RC
or
fO
=
1
2pRC
(12)
where R is equal to RWA such that:
R
=
256 – D
256
R AB
(13)
At resonance, setting
R2
R1
=
2
(14)
balances the bridge. In practice, R2/R1 should be set slightly larger
than 2 to ensure the oscillation can start. On the other hand, the
alternate turn-on of the diodes D1 and D2 ensures R2/R1 to be
smaller than 2 momentarily and therefore stabilizes the oscillation.
Once the frequency is set, the oscillation amplitude can be tuned
by R2B since:
2
3 VO
=
I D R2B
+ VD
(15)
–16–
REV. 0










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