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PDF ( 数据手册 , 数据表 ) AD5161

零件编号 AD5161
描述 256-Position SPI/I2C Selectable Digital Potentiometer
制造商 Analog Devices
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AD5161 数据手册, 描述, 功能
Data Sheet
FEATURES
256-position
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact MSOP-10 (3 mm × 4.9 mm) package
Pin selectable SPI/I2C compatible interface
Extra package address decode pin AD0
Full read/write of wiper register
Power-on preset to midscale
Single supply 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/°C
Low power, IDD = 8 µA
Wide operating temperature −40°C to +125°C
SDO output allows multiple device daisy-chaining
Evaluation board available
APPLICATIONS
Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Gain control and offset adjustment
GENERAL DESCRIPTION
The AD5161 provides a compact 3 mm × 4.9 mm packaged
solution for 256-position adjustment applications. These
devices perform the same electronic adjustment function as
mechanical potentiometers or variable resistors, with enhanced
resolution, solid-state reliability, and superior low temperature
coefficient performance.
The wiper settings are controllable through a pin selectable SPI
or I2C compatible digital interface, which can also be used to
read back the wiper register content. When the SPI mode is
used, the device can be daisy-chained (SDO to SDI), allowing
several parts to share the same control lines. In the I2C mode,
address pin AD0 can be used to place up to two devices on the
same bus. In this same mode, command bits are available to
reset the wiper position to midscale or to shut down the device
into a state of zero power consumption.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 5 µA allows for usage in portable battery-operated
applications.
256-Position SPI/I2C Selectable
Digital Potentiometer
AD5161
FUNCTIONAL BLOCK DIAGRAM
VDD SDO/NC
SDI/SDA
CLK/SCL
DIS
CS/AD0
SPI OR I2C
INTERFACE
A
W
WIPER
REGISTER
B
GND
Figure 1.
PIN CONFIGURATION
A1
10 W
B 2 AD5161 9 VDD
CS/ADO 3 TOP VIEW 8 DIS
SDO/NC 4 (Not to Scale) 7 GND
SDI/SDA 5
6 CLK/SCL
Figure 2.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2012 Analog Devices, Inc. All rights reserved.







AD5161 pdf, 数据表
AD5161
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8 5V
3V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
32 64
96 128 160 192 224 256
CODE (Decimal)
Figure 4. R-INL vs. Code vs. Supply Voltages
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
5V
3V
–0.8
–1.0
0 32 64 96 128 160 192 224 256
CODE (Decimal)
Figure 5. R-DNL vs. Code vs. Supply Voltages
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
32 64
_40°C
+25°C
+85°C
+125°C
96 128 160 192 224 256
CODE (Decimal)
Figure 6. INL vs. Code, VDD = 5 V
Data Sheet
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
–40°C
+25°C
+85°C
+125°C
32 64 96 128 160 192 224 256
CODE (Decimal)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
Figure 7. DNL vs. Code, VDD = 5 V
5V
3V
32 64 96 128 160 192 224 256
CODE (Decimal)
Figure 8. INL vs. Code vs. Supply Voltages
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
5V
3V
32 64 96 128 160 192 224 256
CODE (Decimal)
Figure 9. DNL vs. Code vs. Supply Voltages
Rev. B | Page 8 of 20







AD5161 equivalent, schematic
AD5161
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A-B, W-A, and W-B can be at either
polarity.
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across terminal AB divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at VW with respect to ground for any valid input
voltage applied to terminals A and B is
VW
(D )
=
D
256
V
A
+
256 D
256
VB
(3)
For a more accurate calculation, which includes the effect of
wiper resistance, VW, can be found as
VW
(D )
=
RWB (D)
256
VA
+
RWA (D
256
)
VB
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
PIN SELECTABLE DIGITAL INTERFACE
The AD5161 provides the flexibility of a selectable interface.
When the digital interface select (DIS) pin is tied low, the SPI
mode is engaged. When the DIS pin is tied high, the I2C mode
is engaged.
SPI Compatible 3-Wire Serial Bus (DIS = 0)
The AD5161 contains a 3-wire SPI compatible digital interface
(SDI, CS, and CLK). The 8-bit serial word must be loaded MSB
first. The format of the word is shown in Table 6.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When CS is low, the clock
loads data into the serial register on each positive clock edge
(see Figure 37).
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5161 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
Extra MSB bits are ignored.
Data Sheet
Daisy-Chain Operation
The serial data output (SDO) pin contains an open-drain
N-channel FET. This output requires a pull-up resistor in order
to transfer data to the next package’s SDI pin. This allows for
daisy-chaining several RDACs from a single processor serial
data line. The pull-up resistor termination voltage can be larger
than the VDD supply voltage. It is recommended to increase the
clock period when using a pull-up resistor to the SDI pin of the
following device because capacitive loading at the daisy-chain
node SDO-SDI between devices may induce time delay to
subsequent devices. Users should be aware of this potential
problem to achieve data transfer successfully (see Figure 43). If
two AD5161s are daisy-chained, a total of at least 16 bits of data
is required. The first eight bits, complying with the format
shown in Table 6, go to U2 and the second eight bits with the
same format go to U1. CS should be kept low until all 16 bits are
clocked into their respective serial registers. After this, CS is
pulled high to complete the operation and load the RDAC latch.
If the data word during the CS low period is greater than 16
bits, any additional MSBs will be discarded.
VDD
µC
MOSI
CLK SC
AD5161
U1
SDI
CS
SDO
CLK
RP
2.2k
AD5161
U2
SDI SDO
CS CLK
Figure 43. Daisy-Chain Configuration
I2C Compatible 2-Wire Serial Bus (DIS = 1)
The AD5161 can also be controlled via an I2C compatible serial
bus with DIS tied high. The RDACs are connected to this bus as
slave devices.
The first byte of the AD5161 is a slave address byte (see Table 7
and Table 8). It has a 7-bit slave address and a R/W bit. The six
MSBs of the slave address are 010110, and the following bit is
determined by the state of the AD0 pin of the device. AD0
allows the user to place up to two of the I2C compatible devices
on one bus.
The 2-wire I2C serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 40). The
following byte is the slave address byte, which consists of
the 7-bit slave address followed by an R/W bit (this bit
determines whether data will be read from or written to
the slave device).
Rev. B | Page 16 of 20










页数 20 页
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