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PDF ( 数据手册 , 数据表 ) AD7278

零件编号 AD7278
描述 12-/10-/8-Bit ADCs
制造商 Analog Devices
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AD7278 数据手册, 描述, 功能
FEATURES
Throughput rate: 3 MSPS
Specified for VDD of 2.35 V to 3.6 V
Power consumption
12.6 mW at 3 MSPS with 3 V supplies
Wide input bandwidth
70 dB SNR at 1 MHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Temperature range: −40°C to +125°C
Power-down mode: 0.1 μA typical
6-lead TSOT package
8-lead MSOP package
AD7476 and AD7476A pin-compatible
GENERAL DESCRIPTION
The AD7276/AD7277/AD7278 are 12-/10-/8-bit, high speed,
low power, successive approximation analog-to-digital converters
(ADCs), respectively. The parts operate from a single 2.35 V
to 3.6 V power supply and feature throughput rates of up to
3 MSPS. The parts contain a low noise, wide bandwidth track-
and-hold amplifier that can handle input frequencies in excess
of 55 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS, and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.
The AD7276/AD7277/AD7278 use advanced design techniques
to achieve very low power dissipation at high throughput rates.
The reference for the part is taken internally from VDD. This
allows the widest dynamic input range to the ADC; therefore,
the analog input range for the part is 0 to VDD. The conversion
rate is determined by the SCLK.
3 MSPS, 12-/10-/8-Bit
ADCs in 6-Lead TSOT
AD7276/AD7277/AD7278
FUNCTIONAL BLOCK DIAGRAM
VDD
12-/10-/8-BIT
VIN
SUCCESSIVE
T/H APPROXIMATION
ADC
AD7276/
AD7277/
AD7278
CONTROL
LOGIC
SCLK
SDATA
CS
GND
Figure 1.
Table 1.
Part Number
AD7276
AD7277
AD7278
AD72741
AD72731
Resolution
12
10
8
12
10
Package
8-Lead MSOP 6-Lead TSOT
8-Lead MSOP 6-Lead TSOT
8-Lead MSOP 6-Lead TSOT
8-Lead MSOP 8-Lead TSOT
8-Lead MSOP 8-Lead TSOT
1 Part contains external reference pin.
PRODUCT HIGHLIGHTS
1. 3 MSPS ADCs in a 6-lead TSOT package.
2. AD7476/AD7477/AD7478 and AD7476A/AD7477A/
AD7478A pin-compatible.
3. High throughput with low power consumption.
4. Flexible power/serial clock speed management. This allows
maximum power efficiency at low throughput rates.
5. Reference derived from the power supply.
6. No pipeline delay. The parts feature a standard successive
approximation ADC with accurate control of the sampling
instant via a CS input and once-off conversion control.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005–2011 Analog Devices, Inc. All rights reserved.







AD7278 pdf, 数据表
AD7276/AD7277/AD7278
AD7278 SPECIFICATIONS
VDD = 2.35 V to 3.6 V, fSCLK = 48 MHz, fSAMPLE = 3 MSPS, TA = TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)3
Total Harmonic Distortion (THD)3
Peak Harmonic or Spurious Noise (SFDR)3
Intermodulation Distortion (IMD)3
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity3
Differential Nonlinearity3
Offset Error3
Gain Error3
Total Unadjusted Error (TUE)3
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN4
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time3
Throughput Rate
A Grade1, 2 B Grade1, 2 Unit
49 49 dB min
−66 −67 dB max
−73 −73 dB typ
−69 −69 dB typ
Test Conditions/Comments
fIN = 1 MHz sine wave
−76
−76
dB typ
fa = 1 MHz, fb = 0.97 MHz
−76
−76
dB typ
fa = 1 MHz, fb = 0.97 MHz
5 5 ns typ
18 18 ps typ
74
74
MHz typ
@ 3 dB
10
10
MHz typ
@ 0.1 dB
8 8 Bits
±0.2 ±0.2 LSB max
±0.3
±0.3
LSB max
Guaranteed no missed codes to 8 bits
±0.9 ±0.5 LSB max
±1.2 ±1
LSB max
±1.5 ±1.5 LSB max
0 to VDD
±1
±5.5
42
10
0 to VDD
±1
±5.5
42
10
V
μA max
μA max
pF typ
pF typ
−40°C to +85°C
85°C to 125°C
When in track
When in hold
1.7
1.7
V min
2.35 V ≤ VDD ≤ 2.7 V
2
2
V min
2.7 V < VDD ≤ 3.6 V
0.7
0.7
V max
2.35 V ≤ VDD ≤ 2.7 V
0.8
0.8
V max
2.7 V < VDD ≤ 3.6 V
±1 ±1 μA max
2 2 pF typ
VDD − 0.2
VDD − 0.2
V min
0.2 0.2 V max
±2.5 ±2.5 μA max
4.5 4.5 pF typ
Straight (natural) binary
ISOURCE = 200 μA, VDD = 2.35 V to 3.6 V
ISINK = 200 μA
208
208
ns max
10 SCLK cycles with SCLK at 48 MHz
60 60 ns min
4 4 MSPS max SCLK at 48 MHz
Rev. C | Page 7 of 28







AD7278 equivalent, schematic
TERMINOLOGY
Integral Nonlinearity
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. For the AD7276/
AD7277/AD7278, the endpoints of the transfer function are
zero scale at 0.5 LSB below the first code transition and full
scale at 0.5 LSB above the last code transition.
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
The deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, that is, AGND + 0.5 LSB.
Gain Error
The deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal after adjusting for the offset error,
that is, VREF − 1.5 LSB.
Total Unadjusted Error
A comprehensive specification that includes gain, linearity, and
offset errors.
Track-and-Hold Acquisition Time
The time required after the conversion for the output of the
track-and-hold amplifier to reach its final value within ±0.5 LSB.
See the Serial Interface section for more details.
Signal-to-Noise + Distortion Ratio (SINAD)
The measured ratio of signal to noise plus distortion at the
output of the ADC. The signal is the rms amplitude of the
fundamental, and noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), including
harmonics but excluding dc. The ratio is dependent on the
number of quantization levels in the digitization process: the
more levels, the smaller the quantization noise. For an ideal
N-bit converter, the SINAD is defined as
SINAD = 6.02 N + 1.76 dB
According to this equation, the SINAD is 74 dB for a 12-bit
converter and 62 dB for a 10-bit converter. However, various
error sources in the ADC, including integral and differential
nonlinearities and internal ac noise sources, cause the measured
SINAD to be less than its theoretical value.
AD7276/AD7277/AD7278
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. It is
defined as:
THD (dB) = 20 log V22 + V32 + V42 + V52 + V62
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through sixth harmonics.
Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2, excluding dc) to the rms value
of the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum; however, for
ADCs with harmonics buried in the noise floor, it is determined
by a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb, where
m and n = 0, 1, 2, 3, …. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second-order terms include (fa + fb) and (fa − fb), and the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and
(fa − 2fb).
The AD7276/AD7277/AD7278 are tested using the CCIF
standard in which two input frequencies are used (see fa and fb
in the specifications). In this case, the second-order terms are
usually distanced in frequency from the original sine waves, and
the third-order terms are usually at a frequency close to the input
frequencies. As a result, the second- and third-order terms are
specified separately. The intermodulation distortion is
calculated in a similar manner to the THD specification, that is,
the ratio of the rms sum of the individual distortion products to
the rms amplitude of the sum of the fundamentals expressed in
decibels.
Aperture Delay
The measured interval between the leading edge of the sampling
clock and the point at which the ADC takes the sample.
Aperture Jitter
The sample-to-sample variation when the sample is taken.
Rev. C | Page 15 of 28










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