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PDF ( 数据手册 , 数据表 ) AD7265

零件编号 AD7265
描述 Differential Input/ Dual 1 MSPS/ 12-Bit/ 3-Channel SAR ADC
制造商 Analog Devices
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AD7265 数据手册, 描述, 功能
Preliminary Technical Data
FEATURES
Dual 12-bit, 3-channel ADC
Fast throughput rate: 1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low power: 7 mW max at 1 MSPS with 3 V supplies
16.5 mW max at 1 MSPS with 5 V supplies
Wide input bandwidth
70 dB SNR at 100 kHz input frequency
On-chip reference: 2.5 V
–40°C to +125°C operation
Flexible power/throughput rate management
Simultaneous conversion/read
No pipeline delays
High speed serial interface SPI®/QSPI™/MICROWIRE™/DSP
compatible
Shutdown mode: 1 µA max
32-lead LFCSP and TQFP packages
GENERAL DESCRIPTION
The AD7265 is a dual, 12-bit, high speed, low power, successive
approximation ADC that operates from a single 2.7 V to 5.25 V
power supply and features throughput rates up to 1 MSPS. The
device contains two ADCs, each preceded by a 3-channel multi-
plexer, and a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 10 MHz.
The conversion process and data acquisition are controlled using
standard control inputs, allowing easy interfacing to microproces-
sors or DSPs. The input signal is sampled on the falling edge of CS;
conversion is also initiated at this point. The conversion time is
determined by the SCLK frequency. There are no pipelined delays
associated with the part.
The AD7265 uses advanced design techniques to achieve very low
power dissipation at high throughput rates. With 5 V supplies and a
1 MSPS throughput rate, the part consumes ? mA maximum. The
part also offers flexible power/throughput rate management when
operating in sleep mode.
The analog input range for the part can be selected to be a 0 V to
VREF range or a 2VREF range with either straight binary or twos
complement output coding. The AD7265 has an on-chip 2.5 V
reference that can be overdriven if an external reference is pre-
ferred. This external reference range is 100 mV to 2.5 V. The
AD7265 is available in 32-lead lead frame chip scale (LFCSP) and
thin flat quad (TQFP) lead package.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Differential Input, Dual 1 MSPS,
12-Bit, 3-Channel SAR ADC
AD7265
VA1
VA2
VA3
VA4
VA5
VA6
VB1
V
B2
VB3
VB4
VB5
VB6
FUNCTIONAL BLOCK DIAGRAM
REF SELECT
DcapA
AVdd DVdd
REF
BUF
MUX
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
AD7265
OUTPUT
DRIVERS
CONTROL
LOGIC
12-BIT
T/H SUCCESSIVE
APPROXIMATION
MUX
ADC
OUTPUT
DRIVERS
DOUTA
SCLK
+5
RANGE
DIFF/SE
A0
A1
A2
VDRIVE
DOUTB
BUF
AGND AGND AGND DcapB
DGND
DGND
Figure 1
PRODUCT HIGHLIGHTS
1. The AD7265 features two complete ADC functions that allow
simultaneous sampling and conversion of two channels. Each
ADC has 2 analog inputs, 3 fully differential pairs, or 6 single-
ended channels as programmed. The conversion result of both
channels is available simultaneously on separate data lines, or
in succession on one data line if only one serial port is
available.
2. High Throughput with Low Power Consumption
The AD7265 offers a 1 MSPS throughput rate with ? mW
maximum power consumption when operating at 3 V.
3. Flexible Power/Throughput Rate Management
The conversion rate is determined by the serial clock, allowing
power consumption to be reduced as conversion time is re-
duced through an SCLK frequency increase. Power efficiency
can be maximized at lower throughput rates if the part enters
sleep between conversions.
4. No Pipeline Delay
The part features two standard successive approximation
ADCs with accurate control of the sampling instant via a CS
input and once off conversion control.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.







AD7265 pdf, 数据表
AD7265
TERMINOLOGY
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Offset Error
This applies to Straight Binary output coding. It is the deviation
of the first code transition (00 . . . 000) to (00 . . . 001) from the
ideal, i.e., AGND + 1 LSB.
Offset Error Match
This is the worst case difference in Offset Error between any of
the twelve channels.
Gain Error
This applies to Straight Binary output coding. It is the deviation
of the last code transition (111 . . . 110) to (111 . . . 111) from the
ideal (i.e., VREF – 1 LSB) after the offset error has been adjusted
out.
Gain Error Match
This is the difference in Gain Error between the two channels.
Zero Code Error
This applies when using twos complement output coding in
particular with the 2 x VREF input range as –VREF to +VREF biased
about the VREF point. It is the deviation of the midscale
transition (all 1s to all 0s) from the ideal VIN voltage, i.e., VREF - 1
LSB.
Zero Code Error Match
This refers to the difference in Zero Code Error between the
two channels.
Positive Gain Error
This applies when using twos complement output coding in
particular with the 2 x VREF input range as –VREF to +VREF biased
about the VREF point. It is the deviation of the last code
transition (011…110) to (011…111) from the ideal (i.e., + VREF -
1 LSB) after the Zero Code Error has been adjusted out.
Preliminary Technical Data
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode after the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all non-fundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in
the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7265 it is defined as:
THD(dB) = 20 log V22 + V32 + V42 + V52 + V62
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it will
be a noise peak.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale (2 x VREF), 455kHz sine wave signal to all unselected input
channels and determining how much that signal is attenuated in
the selected channel with a 10 kHz signal (0 V to VREF). The
figure given is the worst-case across all twelve channels for the
AD7265.
Rev. PrA | Page 8 of 16







AD7265 equivalent, schematic
AD7265
ORDERING GUIDE
AD7265 Products
AD7265ACP
AD7265BCP
AD7265ASU
AD7265BSU
EVAL-AD7265CB1
EVAL-CONTROL BRD22
Temperature Package
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Preliminary Technical Data
Package Description
Lead Frame Chip Scale Package
Lead Frame Chip Scale Package
Thin Quad Flat Package
Thin Quad Flat Package
Evaluation Board
Controller Board
Package Outline
CP-32
CP-32
SU-32
SU-32
1 This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL Board for evaluation/demonstration purposes.
2 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete
evaluation kit, the particular ADC evaluation board, e.g., EVAL-AD7265CB, the EVAL-CONTROL BRD2, and a 12V transformer must be ordered. See relevant Evaluation
Board Technical note for more information.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR04674–0–1/04(PrA)
Rev. PrA | Page 16 of 16










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