DataSheet8.cn


PDF ( 数据手册 , 数据表 ) AD724

零件编号 AD724
描述 RGB to NTSC/PAL Encoder
制造商 Analog Devices
LOGO Analog Devices LOGO 


1 Page

No Preview Available !

AD724 数据手册, 描述, 功能
a
RGB to NTSC/PAL Encoder
AD724
FEATURES
Low Cost, Integrated Solution
+5 V Operation
Accepts FSC Clock or Crystal, or 4FSC Clock
Composite Video and Separate Y/C (S-Video) Outputs
Luma and Chroma Outputs Are Time Aligned
Minimal External Components:
No External Filters or Delay Lines Required
Onboard DC Clamp
Accepts Either HSYNC and VSYNC or CSYNC
Phase Lock to External Subcarrier
Drives 75 Reverse-Terminated Loads
Logic Selectable NTSC or PAL Encoding Modes
Compact 16-Lead SOIC
APPLICATIONS
RGB to NTSC or PAL Encoding
PRODUCT DESCRIPTION
The AD724 is a low cost RGB to NTSC/PAL Encoder that
converts red, green and blue color component signals into their
corresponding luminance (baseband amplitude) and chromi-
nance (subcarrier amplitude and phase) signals in accordance
with either NTSC or PAL standards. These two outputs are also
combined to provide composite video output. All three outputs can
simultaneously drive 75 , reverse-terminated cables. All logi-
cal inputs are TTL, 3 V and 5 V CMOS compatible. The chip
operates from a single +5 V supply. No external delay lines or
filters are required. The AD724 may be powered down when
not in use.
The AD724 accepts either FSC or 4FSC clock. When a clock is
not available, a low cost parallel-resonant crystal (3.58 MHz
(NTSC) or 4.43 MHz (PAL)) and the AD724’s on-chip oscilla-
tor generate the necessary subcarrier clock. The AD724 also
accepts the subcarrier clock from an external video source.
The interface to graphics controllers is simple: an on-chip logic
“XNOR” accepts the available vertical (VSYNC) and horizon-
tal sync (HSYNC) signals and creates the composite sync
(CSYNC) signal on-chip. If available, the AD724 will also
accept a standard CSYNC signal by connecting VSYNC to
Logic HI and applying CSYNC to the HSYNC pin. The
AD724 contains decoding logic to identify valid horizontal sync
pulses for correct burst insertion.
Delays in the U and V chroma filters are matched by an on-chip
sampled-data delay line in the Y signal path. To prevent alias-
ing, a prefilter at 5 MHz is included ahead of the delay line and
a post-filter at 5 MHz is added after the delay line to suppress
harmonics in the output. These low-pass filters are optimized
for minimum pulse overshoot. The overall luma delay, relative
to chroma, has been designed to be time aligned for direct input to
a television’s baseband. The AD724 comes in a space-saving
SOIC and is specified for the 0°C to +70°C commercial tem-
perature range.
FUNCTIONAL BLOCK DIAGRAM
SUB-
CARRIER
FSC
4FSC
NTSC/PAL
HSYNC
VSYNC
4FSC
XNOR
4FSC
XOSC
PHASE
DETECTOR
CHARGE
PUMP
SYNC
SEPARATOR
CSYNC
QUADRATURE
+4
DECODER
FSC
CSYNC
BURST
FSC 90°
FSC 0°
CSYNC
LOOP
FILTER
4FSC
VCO
NTSC/PAL
±180°
SC 90°/270°
(PAL ONLY)
CLOCK
AT 8FSC
RED
GREEN
BLUE
DC
CLAMP
DC
CLAMP
DC
CLAMP
Y 3-POLE
LP PRE-
FILTER
RGB-TO-YUV
ENCODING
MATRIX
U
4-POLE
LPF
V 4-POLE
LPF
U
CLAMP
V
CLAMP
SAMPLED-
DATA
DELAY LINE
2-POLE
LP POST-
FILTER
NTSC/PAL
BALANCED
MODULATORS
4-POLE
LPF
X2
LUMINANCE
OUTPUT
X2
COMPOSITE
OUTPUT
X2
CHROMINANCE
OUTPUT
BURST
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999







AD724 pdf, 数据表
AD724
THEORY OF OPERATION
The AD724 was designed to have three allowable modes of
applying a clock via the FIN pin. These are FSC (frequency of
subcarrier) mode with CMOS clock applied, FSC mode using
on-chip crystal oscillator, and 4FSC mode with CMOS clock
applied. The FSC frequency is 3.579545 MHz for NTSC or
4.433618 MHz for PAL.
To use FSC mode the SELECT pin is pulled low and either a
CMOS FSC clock is applied to FIN, or a parallel-resonant
crystal and appropriate tuning capacitor is placed between the
FIN pin and AGND to utilize the on-chip oscillator. The on-
chip Phase Locked Loop (PLL) is used in these modes to gener-
ate an internal 4FSC clock that is divided to perform the digital
timing as well as create the quadrature subcarrier signals for the
chrominance modulation.
In 4FSC mode, the SELECT pin is pulled high and the PLL is
bypassed.
Referring to the AD724 block diagram (Figure 14), the RGB
inputs (each 714 mV p-p max) are dc clamped using external
coupling capacitors. These clamps allow the user to have a black
level that is not at 0 V. The clamps will adjust to an on-chip
black input signal level of approximately 0.8 V. This clamping
occurs on the back porch during the burst period.
The RGB inputs then pass into an analog encoding matrix,
which creates the luminance (“Y”) signal and the chrominance
color difference (“U” and “V”) signals. The RGB to YUV en-
coding is performed using the following standard transformations:
Y = 0.299 × R + 0.587 × G + 0.114 × B
U = 0.493 × (BY)
V = 0.877 × (RY)
After the encoding matrix, the AD724 has two parallel analog
paths. The Y (luminance) signal is first passed through a 3-pole
4.85 MHz/6 MHz (NTSC/PAL) Bessel low-pass filter to pre-
vent aliasing in the sampled-data delay line. In this first low-pass
filter, the unclocked sync is injected into the Y signal. The Y
signal then passes through the sampled-data delay line, which is
clocked at 8FSC. The delay line was designed to match the
overall chrominance and luminance delays. Following the
sampled-data delay line is a 5.25 MHz/6.5 MHz (NTSC/PAL)
2-pole low-pass Bessel filter to smooth the reconstructed lumi-
nance signal.
The second analog path is the chrominance path in which the U
and V color difference signals are processed. The U and V sig-
nals first pass through 4-pole modified Bessel low-pass filters
with –3 dB frequencies of 1.2 MHz/1.5 MHz (NTSC/PAL) to
prevent aliasing in the modulators. The color burst levels are
injected into the U channel for NTSC (U and V for PAL) in
these premodulation filters. The U and V signals are then inde-
pendently modulated by a pair of balanced switching modula-
tors driven in quadrature by the color subcarrier.
The bandwidths of the on-chip filters are tuned using propri-
etary auto-tuning circuitry. The basic principle is to match an
RC time constant to a reference time period, that time being
one cycle of a subcarrier clock. The auto-tuning is performed
during the vertical blanking interval and has added hysteresis so
that once an acceptable tuning value is reached the part won’t
toggle tuning values from field to field. The bandwidths stated
in the above discussion are the design target bandwidths for
NTSC and PAL.
The AD724’s 4FSC clock (either produced by the on-chip PLL
or user supplied) drives a digital divide-by-four circuit to create
the quadrature signals for modulation. The reference phase 0° is
used for the U signal. In the NTSC mode, the V signal is modu-
lated at 90°, but in PAL mode, the V modulation alternates
between 90° and 270° at the horizontal line rate as required by
the PAL standard. The outputs of the U and V balanced modu-
lators are summed and passed through a 3-pole low-pass filter with
3.6 MHz/4.4 MHz bandwidths (NTSC/PAL) in order to re-
move the harmonics generated during the switching modulation.
SUB- FSC
CARRIER
4FSC
NTSC/PAL
HSYNC
VSYNC
XOSC
PHASE
DETECTOR
CHARGE
PUMP
4FSC
SYNC
SEPARATOR
XNOR
CSYNC
4FSC
QUADRATURE
+4
DECODER
FSC
CSYNC
BURST
FSC 90؇
FSC 0؇
CSYNC
LOOP
FILTER
4FSC
VCO
NTSC/PAL
±180؇
SC 90؇/270؇
(PAL ONLY)
CLOCK
AT 8FSC
RED
DC
CLAMP
Y 3-POLE
LP PRE-
FILTER
SAMPLED-
DATA
DELAY LINE
GREEN
BLUE
DC
CLAMP
DC
CLAMP
RGB-TO-YUV
ENCODING
MATRIX
U
4 -POLE
LPF
V 4-POLE
LPF
U
CLAMP
V
CLAMP
BALANCED
MODULATORS
BURST
Figure 14. Functional Block Diagram
POWER AND GROUNDS
+5V LOGIC
+5V ANALOG
AGND
ANALOG
DGND
LOGIC
NOTE:
THE LUMINANCE, COMPOSITE, AND
CHROMINANCE OUTPUTS ARE AT
TWICE NORMAL LEVELS FOR DRIVING
75REVERSE-TERMINATED LINES.
2-POLE
LP POST-
FILTER
NTSC/PAL
4-POLE
LPF
X2
LUMINANCE
OUTPUT
X2
COMPOSITE
OUTPUT
CHROMINANCE
X2 OUTPUT
–8– REV. B














页数 15 页
下载[ AD724.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
AD720RGB to NTSC/PAL EncodersAnalog Devices
Analog Devices
AD721RGB to NTSC/PAL EncodersAnalog Devices
Analog Devices
AD7216N2LAC-DC / External Freestanding AdapterEmerson
Emerson
AD722RGB to NTSC/PAL EncoderAnalog Devices
Analog Devices

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap