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PDF ( 数据手册 , 数据表 ) AD652

零件编号 AD652
描述 Monolithic Synchronous Voltage-to-Frequency Converter
制造商 Analog Devices
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AD652 数据手册, 描述, 功能
a
FEATURES
Full-Scale Frequency (Up to 2 MHz) Set by External
System Clock
Extremely Low Linearity Error (0.005% max at 1 MHz
FS, 0.02% max at 2 MHz FS)
No Critical External Components Required
Accurate 5 V Reference Voltage
Low Drift (25 ppm/؇C max)
Dual or Single Supply Operation
Voltage or Current Input
MIL-STD-883 Compliant Versions Available
Monolithic Synchronous
Voltage-to-Frequency Converter
AD652
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTION
The AD652 Synchronous Voltage-to-Frequency Converter
(SVFC) is a powerful building block for precision analog-to-
digital conversion, offering typical nonlinearity of 0.002%
(0.005% maximum) at a 100 kHz output frequency. The inher-
ent monotonicity of the transfer function and wide range of
clock frequencies allows the conversion time and resolution to
be optimized for specific applications.
The AD652 uses a variation of the popular charge-balancing
technique to perform the conversion function. The AD652 uses
an external clock to define the full-scale output frequency,
rather than relying on the stability of an external capacitor. The
result is a more stable, more linear transfer function, with sig-
nificant application benefits in both single- and multichannel
systems.
Gain drift is minimized using a precision low drift reference and
low TC on-chip thin-film scaling resistors. Furthermore, the ini-
tial gain error is reduced to less than 0.5% by the use of
laser-wafer-trimming.
The analog and digital sections of the AD652 have been de-
signed to allow operation from a single-ended power source,
simplifying its use with isolated power supplies.
The AD652 is available in five performance grades. The 20-lead
PLCC packaged JP and KP grades are specified for operation
over the 0°C to +70°C commercial temperature range. The
16-lead cerdip-packaged AQ and BQ grades are specified for
operation over the –40°C to +85°C industrial temperature
range, and the AD652SQ is available for operation over the full
–55°C to +125°C extended temperature range.
PRODUCT HIGHLIGHTS
1. The use of an external clock to set the full-scale frequency
allows the AD652 to achieve linearity and stability far supe-
rior to other monolithic VFCs. By using the same clock to
drive the AD652 and (through a suitable divider) also set the
counting period, conversion accuracy is maintained indepen-
dent of variations in clock frequency.
2. The AD652 Synchronous VFC requires only a single external
component (a noncritical integrator capacitor) for operation.
3. The AD652 includes a buffered, accurate 5 V reference
which is available to the user.
4. The clock input of the AD652 is TTL and CMOS compat-
ible and can also be driven by sources referred to the negative
power supply. The flexible open-collector output stage pro-
vides sufficient current sinking capability for TTL and CMOS
logic, as well as for optical couplers and pulse transformers.
A capacitor-programmable one-shot is provided for selection
of optimum output pulse width for power reduction.
5. The AD652 can also be configured for use as a synchronous
F/V converter for isolated analog signal transmission.
6. The AD652 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD652/883B data sheet for detailed
specifications.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000







AD652 pdf, 数据表
AD652
adjustment is then accomplished using a 500 series trimmer.
See Figures 10a and 10b. When negative input voltages are
used, this 500 trimmer will be tied to ground and Pin 6 will
be the input pin.
This gain trim should be done with an input voltage of 9 V, and
the output frequency should be adjusted to exactly 45% of the
clock frequency. Since the device settles into a divide-by-two
mode for an input overrange condition, adjusting the gain with a
10 V input is impractical; the output frequency would be exactly
one-half the clock frequency if the gain were too high and would
not change with adjustment until the exact proper scale factor
was achieved. Hence, the gain adjustment should be done with a
9 V input.
The offset of the op amp may be trimmed to zero with the trim
scheme shown in Figures 10a for the cerdip packaged device and
Figure 10b for the PLCC packaged device. One way of trim-
ming the offset is by grounding Pin 7 (8) of the cerdip (PLCC)
packaged device and observing the waveform at Pin 4. If the off-
set voltage of the op amp is positive, then the integrator will have
saturated and the voltage will be at the positive rail. If the offset
voltage is negative, then there will be a small effective input current
that will cause the AD652 to oscillate and a sawtooth waveform
will be observed at Pin 4. The trimpot should be adjusted until
the downward slope of this sawtooth becomes very slow, down
to a frequency of 1 Hz or less. In an analog-to-digital conversion
application, an easier way to trim the offset is to apply a small
input voltage, such as 0.01% of the full-scale voltage, and adjust
the trimpot until the correct digital output is reached.
GAIN PERFORMANCE
The AD652 gain error is specified as the difference in slope
between the actual and the ideal transfer function over the full-
scale frequency range. Figure 11 shows a plot of the typical
gain error changes vs. the clock input frequency, normalized
to 100 kHz. If after using the AD652 with a full-scale clock
frequency of 100 kHz it is decided to reduce the necessary gat-
ing time by increasing the clock frequency, this plot shows the
typical gain changes normalized to the original 100 kHz gain.
reference voltage. For example, a 10 mA load interacting with
a 0.3 typical output impedance will change the reference
voltage by 0.06%.
DIGITAL INTERFACING CONSIDERATIONS
The AD652 clock input is a high impedance input with a
threshold voltage of two diode voltages with respect to Digital
Ground at Pin 12 (approximately 1.2 volts at room temp).
When the clock input is low, 5 µA10 µA flows out of this pin.
When the clock input is high, no current flows.
The frequency output is an open collector pull-down and is
capable of sinking 10 mA with a maximum voltage of 0.4 volts.
This will drive 6 standard TTL inputs. The open collector pull
up voltage can be as high as 36 volts above digital ground.
COMPONENT SELECTION
The AD652 integrating capacitor should be 0.02 µF. If a large
amount of normal mode interference is expected (more than
0.1 volts) and the clock frequency is less than 500 kHz, an inte-
grating capacitor of 0.1 µF should be used. Mylar, polypropylene,
or polystyrene capacitors should be used.
The open collector pull-up resistor should be chosen to give
adequately fast rise times. At low clock frequencies (100 kHz)
larger resistor values (several k) and slower rise times may be
tolerated. However, at higher clock frequencies (1 MHz) a lower
value resistor should be used. The loading of the logic input
which is being driven must also be taken into consideration.
For example, if 2 standard TTL loads are to be driven then a
3.2 mA current must be sunk, leaving 6.8 mA for the pull-up
resistor if the maximum low level voltage is to be maintained at
0.4 volts. A 680 resistor would thus be selected ((5 V0.4)V/
6.8 mA) = 680 .
The one-shot capacitor controls the pulse width of the fre-
quency output. The pulse is initiated by the rising edge of the
clock signal. The delay time between the rising edge of the clock
and the falling edge of the frequency output is typically 200 ns.
The width of the pulse is 5 ns/pF and the minimum width is
about 200 ns with Pin 9 floating. If the one-shot period is acci-
dentally chosen longer than the clock period, the width of the
pulse will default to equal the clock period. The one-shot can be
disabled by connecting Pin 9 to +VS (Figure 12); the output
pulse width will then be equal to the clock period. The one-shot
is activated (Figure 13) by connecting a capacitor from Pin 9 to
+VS, VS, or Digital Ground (+VS is preferred).
Figure 11. Gain vs. Clock lnput
REFERENCE NOISE
The AD652 has on board a precision buffered 5 V reference
which is available to the user. Besides being used to offset the
noninverting comparator input in the voltage-to-frequency
mode, this reference can be used for other applications such as
offsetting the input to handle bipolar signals and providing
bridge excitation. It can source 10 mA and sink 100 µA, and is
short circuit protected. Heavy loading of the reference will not
change the gain of the VFC, although it will affect the external
Figure 12. One Shot
Disabled
8
Figure 13. One Shot
Enabled
REV. B







AD652 equivalent, schematic
AD652
Figure 30. Delta Modulator lnput Signal and Ramp-Wise
Approximation
These resistors should be selected such that the following equa-
tion holds:
10 V
= VBRIDGE
2 RF
RG
+ 1
where 10 kΩ ≤ RF 20 k, and VBRIDGE is the maximum
output voltage of the bridge.
The bridge output may be unipolar, as is the case for most
pressure transducers, or it may be bipolar as in some strain mea-
surements. If the signal is unipolar, the reference input of the
AD625 (Pin 7) is simply grounded. If the bridge has a bipolar
output, however, the AD652 reference can be tied to Pin 7,
thereby, converting a ± 5 volt signal (after gain) into a 0 volt to
+10 volt input for the SVFC.
Figure 31. Delta Modulator Input Signal, Ramp-Wise
Approximation and Output Frequency
Figure 32. Maximum Integrating Cap Value vs. Input
Signal Bandwidth
BRIDGE TRANSDUCER INTERFACE
The circuit of Figure 33 illustrates a simple interface between
the AD652 and a bridge-type transducer. The AD652 is an
ideal choice because its buffered 5 volt reference can be used as
the bridge excitation thereby ratiometrically eliminating the gain
drift related errors. This reference will provide a minimum of
10 mA of external current, which is adequate for bridge resis-
tance of 600 and above. If, for example, the bridge resistance
is 120 or 350 , an external pull-up resistor (RPU) is required
and can be calculated using the formula:
RPU (max ) =
+VS 5 V
5V
RBRIDGE
10
mA
An instrumentation amplifier is used to condition the bridge sig-
nal before presenting it to the SVFC. The AD625, with its high
CMRR, minimizes common-mode errors and also can be set to
arbitrary gains between 1 and 10,000 via three resistors, simpli-
fying the scaling for the AD652s calibrated 10 volt input range.
Figure 33. Bridge Transducer Interface
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Cerdip
(Q-16)
0.005 (0.13) MIN
0.080 (2.03) MAX
16 9
0.310 (7.87)
0.220 (5.59)
18
PIN 1
0.840 (21.34) MAX
0.060 (1.52)
0.200 (5.08)
0.015 (0.38)
MAX
0.150
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
(3.81)
MIN
0.070
(1.78)
SEATING
PLANE
0.030 (0.76)
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
15° 0.008 (0.20)
PLCC
(P-20A)
0.180 (4.57)
0.048 (1.21)
0.165 (4.19)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
3 19
4 PIN 1 18
IDENTIFIER
TOP VIEW
(PINS DOWN)
0.050
(1.27)
BSC
0.020
(0.50)
R
8 14
9 13
0.356 (9.04)
0.350 (8.89)SQ
0.395 (10.02)
0.385 (9.78) SQ
0.025 (0.63)
0.015 (0.38)
0.021 (0.53)
0.013 (0.33) 0.330 (8.38)
0.032 (0.81) 0.290 (7.37)
0.026 (0.66)
0.040 (1.01)
0.025 (0.64)
0.110 (2.79)
0.085 (2.16)
16
REV. B










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