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PDF ( 数据手册 , 数据表 ) AD6459

零件编号 AD6459
描述 GSM 3 V Receiver IF Subsystem
制造商 Analog Devices
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AD6459 数据手册, 描述, 功能
a
FEATURES
Fully Compliant with Standard and Enhanced GSM
Specification
–11 dBm Input 1 dB Compression Point
0 dBm Input Third Order Intercept
10 dB SSB Noise Figure (50 )
DC-500 MHz RF and LO Bandwidths
Linear IF Amplifier
Linear-in-dB and Stable over Temperature
Voltage Gain Control
Quadrature Demodulator
On-Board Phase-Locked Quadrature Oscillator
Demodulates IFs from 5 MHz to 50 MHz
Low Power
8 mA at Midgain
2 A Sleep Mode Operation
2.7 V to 5.5 V Operation
Interfaces to AD7013, AD7015 and AD6421 Baseband
Converters
20-Lead SSOP
GSM 3 V Receiver IF Subsystem
AD6459
FUNCTIONAL BLOCK DIAGRAM
LO
RF
GAIN
CONTROL
FREF
BPF
I
PLL
Q
AD6459
GENERAL DESCRIPTION
The AD6459 is a 3 V, low power receiver IF subsystem for
operation at input frequencies as high as 500 MHz and IFs
from 5 MHz up to 50 MHz. It is optimized for operation in
GSM, DCS1800 and PCS1900 receivers. It consists of a mixer,
an IF amplifier, I and Q demodulators, a phase-locked quadra-
ture oscillator, a precise AGC subsystem, and a biasing system
with external power-down.
The AD6459’s low noise, high intercept mixer is a doubly-
balanced Gilbert-Cell type. It has a nominal –11 dBm input-
referred 1 dB compression point and a 0 dBm input-referred
third-order intercept. The mixer section of the AD6459 also
includes a local oscillator (LO) preamplifier, which lowers the
required LO drive to –16 dBm.
The gain control input accepts an external gain-control voltage
input from an external AGC detector or a DAC. It provides an
80 dB gain range with 27 mV/dB gain scaling.
The I and Q demodulators provide in-phase and quadrature
baseband outputs to interface with Analog Devices’ AD7013
(IS54, TETRA, MSAT) AD7015 and AD6421 (GSM,
DCS1800, PCS1900) baseband converters. An on-board
quadrature VCO that is externally phase-locked to the IF signal
drives the I and Q demodulators. This locked reference signal is
normally provided by an external VCTCXO under the control of
the radio’s digital processor. The AD6459 can also provide
demodulation of N-PSK and N-QAM in many non-TDMA
systems when used with external analog carrier recovery systems
such as the Costas Loop. Finally, the VCO can be phase-locked
to a frequency that is deliberately offset from the IF as in the
case of a Beat-Frequency oscillator (BFO) resulting in the
product detection of CW or SSB.
The AD6459 uses supply voltages from 2.7 V to 5.5 V over the
temperature range of –40°C to +85°C. Operation is enabled by a
CMOS logical level; response time is typically < 80 µs. When
disabled, the standby current is reduced to 2 µA.
The AD6459 comes in a 20-pin shrink small outline (SSOP)
surface mount package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996







AD6459 pdf, 数据表
AD6459
PRODUCT OVERVIEW
The AD6459 provides most of the active circuitry required to
realize a complete low power, single-conversion superhetero-
dyne receiver, or the latter part of a double-conversion receiver,
at input frequencies up to 500 MHz, with an IF from 5 MHz to
50 MHz. The internal I/Q demodulators, and their associated
phase-locked loop, support a wide variety of modulation modes,
including n-PSK, n-QAM and GMSK. A single positive supply
voltage of 3 V is required (2.7 V minimum, 5.5 V maximum) at
a typical supply current of 8 mA at midgain. In the following
discussion, VPOS will be used to denote the power supply voltage,
which will be normally assumed to be 3 V.
Figure 20 shows the main sections of the AD6459. It consists of
a variable-gain UHF mixer and a linear two-stage IF strip,
which together provide a calibrated voltage-controlled gain range
of more than 76 dB, followed by dual quadrature demodulators.
These are driven by inphase and quadrature clocks that are
generated by a Phase-Locked Loop (PLL), which is locked to a
corrected external reference. A CMOS-compatible power-down
interface completes the AD6459.
Mixer
The UHF mixer is an improved Gilbert-cell design and can
operate from low frequencies (it is internally dc-coupled) up to
an RF input of 500 MHz. The dynamic range at the input of the
mixer is determined, at the upper end, by the maximum input
signal level of ± 90 mV (–11 dBm in 50 between RFHI and
RFLO) up to which the mixer remains essentially linear, and at
the lower end, by the noise level. It is customary to define the
linearity of a mixer in terms of its 1 dB gain-compression point
and third-order intercept, which for the AD6459 are –11 dBm
and 0 dBm, respectively, in a 50 system.
The mixer’s RF input port is differential; that is, pin RFLO is
functionally identical to RFHI, and these nodes are internally
biased. The RF port can be modeled as a parallel RC circuit as
shown in Figure 19.
RFHI
RFLO
CSH
RSH
Figure 19. Mixer Port Modeled as a Parallel RC Network
The local oscillator (LO) input is internally biased at VP–0.8 V
and must be ac coupled. The LO interface includes a preampli-
fier that minimizes the drive requirements, thus simplifying the
oscillator design and reducing LO leakage from the RF port.
The LO requires a single-sided drive of ± 50 mV, or –16 dBm
in a 50 system. For operation above 300 MHz, noise figure
can be improved by increasing the LO level.
RFHI 6
RFLO 5
VPS1 20
VPS2 18
PRUP 3
LOIP
4
MXOP
9
10
MXOM
LC
BANDPASS
FILTER
IFIP
11
12
IFIM
+
BIAS
CIRCUIT
AGC VOLTAGE
AD6459
2
COM1
7
COM2
0°
PLL
50°
GAIN TO
COMPENSATION
4.7k
17 IRXP
16 IRXN
4.7k
1 FREF
19 FLTR
4.7k
15 QRXP
14 QRXN
4.7k
13 GAIN
8 GREF
Figure 20. Functional Block Diagram
–8– REV. 0














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