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PDF ( 数据手册 , 数据表 ) AD625

零件编号 AD625
描述 Programmable Gain Instrumentation Amplifier
制造商 Analog Devices
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AD625 数据手册, 描述, 功能
a
FEATURES
User Programmed Gains of 1 to 10,000
Low Gain Error: 0.02% Max
Low Gain TC: 5 ppm/؇C Max
Low Nonlinearity: 0.001% Max
Low Offset Voltage: 25 V
Low Noise 4 nV/Hz (at 1 kHz) RTI
Gain Bandwidth Product: 25 MHz
16-Lead Ceramic or Plastic DIP Package,
20-Terminal LCC Package
Standard Military Drawing Available
MlL-Standard Parts Available
Low Cost
Programmable Gain
Instrumentation Amplifier
AD625
FUNCTIONAL BLOCK DIAGRAM
–INPUT
–GAIN
SENSE
–GAIN
DRIVE
50
–+
+GAIN
DRIVE
+GAIN
SENSE
+INPUT
50+
–+
VB
AD625
10k
10k
10k
+
10k
–+
SENSE
OUTPUT
REFERENCE
PRODUCT DESCRIPTION
The AD625 is a precision instrumentation amplifier specifically
designed to fulfill two major areas of application: 1) Circuits re-
quiring nonstandard gains (i.e., gains not easily achievable with
devices such as the AD524 and AD624). 2) Circuits requiring a
low cost, precision software programmable gain amplifier.
For low noise, high CMRR, and low drift the AD625JN is the
most cost effective instrumentation amplifier solution available.
An additional three resistors allow the user to set any gain from
1 to 10,000. The error contribution of the AD625JN is less than
0.05% gain error and under 5 ppm/°C gain TC; performance
limitations are primarily determined by the external resistors.
Common-mode rejection is independent of the feedback resistor
matching.
A software programmable gain amplifier (SPGA) can be config-
ured with the addition of a CMOS multiplexer (or other switch
network), and a suitable resistor network. Because the ON
resistance of the switches is removed from the signal path, an
AD625 based SPGA will deliver 12-bit precision, and can be
programmed for any set of gains between 1 and 10,000, with
completely user selected gain steps.
For the highest precision the AD625C offers an input offset
voltage drift of less than 0.25 µV/°C, output offset drift below
15 µV/°C, and a maximum nonlinearity of 0.001% at G = 1. All
grades exhibit excellent ac performance; a 25 MHz gain band-
width product, 5 V/µs slew rate and 15 µs settling time.
The AD625 is available in three accuracy grades (A, B, C) for
industrial (–40°C to +85°C) temperature range, two grades (J,
K) for commercial (0°C to +70°C) temperature range, and one
(S) grade rated over the extended (–55°C to +125°C) tempera-
ture range.
PRODUCT HIGHLIGHTS
1. The AD625 affords up to 16-bit precision for user selected
fixed gains from 1 to 10,000. Any gain in this range can be
programmed by 3 external resistors.
2. A 12-bit software programmable gain amplifier can be config-
ured using the AD625, a CMOS multiplexer and a resistor
network. Unlike previous instrumentation amplifier designs,
the ON resistance of a CMOS switch does not affect the gain
accuracy.
3. The gain accuracy and gain temperature coefficient of the
amplifier circuit are primarily dependent on the user selected
external resistors.
4. The AD625 provides totally independent input and output
offset nulling terminals for high precision applications. This
minimizes the effects of offset voltage in gain-ranging
applications.
5. The proprietary design of the AD625 provides input voltage
noise of 4 nV/Hz at 1 kHz.
6. External resistor matching is not required to maintain high
common-mode rejection.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000







AD625 pdf, 数据表
AD625
THEORY OF OPERATION
The AD625 is a monolithic instrumentation amplifier based on
a modification of the classic three-op-amp approach. Monolithic
construction and laser-wafer-trimming allow the tight matching
and tracking of circuit components. This insures the high level
of performance inherent in this circuit architecture.
A preamp section (Q1Q4) provides additional gain to A1 and
A2. Feedback from the outputs of A1 and A2 forces the collec-
tor currents of Q1Q4 to be constant, thereby, impressing the
input voltage across RG. This creates a differential voltage at the
outputs of A1 and A2 which is given by the gain (2RF/RG + 1)
times the differential portion of the input voltage. The unity
gain subtracter, A3, removes any common-mode signal from the
output voltage yielding a single ended output, VOUT, referred to
the potential at the reference pin.
The value of RG is the determining factor of the transconduc-
tance of the input preamp stage. As RG is reduced for larger
gains the transconductance increases. This has three important
advantages. First, this approach allows the circuit to achieve a
very high open-loop gain of (3 × 108 at programmed gains 500)
thus reducing gain related errors. Second, the gain-bandwidth
product, which is determined by C3, C4, and the input trans-
conductance, increases with gain, thereby, optimizing frequency
response. Third, the input voltage noise is reduced to a value
determined by the collector current of the input transistors
(4 nV/Hz).
INPUT PROTECTION
Differential input amplifiers frequently encounter input voltages
outside of their linear range of operation. There are two consid-
erations when applying input protection for the AD625; 1) that
continuous input current must be limited to less than 10 mA
and 2) that input voltages must not exceed either supply by
more than one diode drop (approximately 0.6 V @ 25°C).
Under differential overload conditions there is (RG + 100) in
series with two diode drops (approximately 1.2 V) between the
plus and minus inputs, in either direction. With no external protec-
tion and RG very small (i.e., 40 ), the maximum overload
voltage the AD625 can withstand, continuously, is approximately
± 2.5 V. Figure 26a shows the external components necessary to
protect the AD625 under all overload conditions at any gain.
+VS
50A
+
VB
50A
A1
C3
A2
C4
10k
GAIN
DRIVE
GAIN
DRIVE
10k
50
IN
Q1, Q3
RF RF
RG
Q2, Q4
50
50A
GAIN GAIN
SENSE SENSE
50A
10k
10k
+IN
SENSE
VO
REF
VS
Figure 25. Simplified Circuit of the AD625
The diodes to the supplies are only necessary if input voltages
outside of the range of the supplies are encountered. In higher
gain applications where differential voltages are small, back-to-
back Zener diodes and smaller resistors, as shown in Figure
26b, provides adequate protection. Figure 26c shows low cost
FETs with a maximum ON resistance of 300 configured to offer
input protection with minimal degradation to noise, (5.2 nV/Hz
compared to normal noise performance of 4 nV/Hz).
During differential overload conditions, excess current will flow
through the gain sense lines (Pins 2 and 15). This will have no
effect in fixed gain applications. However, if the AD625 is being
used in an SPGA application with a CMOS multiplexer, this
current should be taken into consideration. The current capa-
bilities of the multiplexer may be the limiting factor in allowable
overflow current. The ON resistance of the switch should be
included as part of RG when calculating the necessary input
protection resistance.
+VS
1.4k
+IN
1.4k
IN
FD333 FD333
RF
RG
RF
FD333 FD333
AD625
VOUT
VS
Figure 26a. Input Protection Circuit
+VS
500
+IN
FD333
FD333
1N5837A
RF
1N5837A
RG
RF
500
IN
FD333
AD625
VOUT
FD333
VS
Figure 26b. Input Protection Circuit for G > 5
FD333
+VS
+IN
2k
2N5952
FD333
RF
RG AD625
RF
VOUT
IN
2k
2N5952
FD333
FD333
VS
Figure 26c. Input Protection Circuit
–8– REV. D














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