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PDF ( 数据手册 , 数据表 ) AD6121

零件编号 AD6121
描述 CDMA 3 V Receiver IF Subsystem with Integrated Voltage Regulator
制造商 Analog Devices
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AD6121 数据手册, 描述, 功能
a
CDMA 3 V Receiver IF Subsystem
with Integrated Voltage Regulator
FEATURES
Fully Compliant with IS98A and PCS Specifications
CDMA, W-CDMA, AMPS, and TACS Operation
Linear IF Amplifier
5.9 dB Noise Figure
–47.5 dB to +47 dB Linear-in-dB Gain Control
Quadrature Demodulator
Demodulates IFs from 50 MHz to 350 MHz
Integral Low Dropout Regulator
200 mV Voltage Drop
Accepts 2.9 V to 4.2 V Input from Battery
Low Power
10 mA at Midgain
<1 A Sleep Mode Operation
Companion Transmitter IF Chip Available (AD6122)
APPLICATIONS
CDMA, W-CDMA, AMPS, and TACS Operation
QPSK Receivers
AD6121
GENERAL DESCRIPTION
The AD6121 is a low power receiver IF subsystem specifically
designed for CDMA applications. It consists of high dynamic
range IF amplifiers with voltage controlled gain, a divide-by-two
quadrature generator, an I and Q demodulator, and a power-
down control input. An integral low dropout regulator allows
operation from battery voltages from 2.9 V to 4.2 V.
The gain control input accepts an external gain control voltage
input from a DAC. It provides 94.5 dB of gain control with a
nominal 52.5 dB/V scale factor when using an internal voltage
reference. The gain control interface reference input can be
connected to either the internal reference or an external reference.
The I and Q demodulator provides differential quadrature base-
band outputs to interface with CDMA baseband converters. A
divide-by-two quadrature generator followed by dual polyphase
filters ensures maximum ± 2.5° quadrature accuracy.
The AD6121 IF Subsystem is fabricated using a 25 GHz ft
BiCMOS silicon process and is packaged in a 28-lead SSOP
and a 32-leadless LPCC chip scale package (5 mm × 5 mm).
FUNCTIONAL BLOCK DIAGRAM
ROOFING
FILTER
CDMA
INPUT
FM
INPUT
IF
OUTPUT
DEMODULATOR
INPUT
IF AMPLIFIERS
INPUT STAGE
PTAT
TEMPERATURE
COMPENSATION
I
2
AD6121
Q
QUADRATURE DEMODULATOR
IOUT
IOUT
LOCAL
OSCILLATOR
INPUT
QOUT
QOUT
GAIN CONTROL
SCALE FACTOR
VREG
LOW
DROPOUT
REGULATOR
VPOS
CDMA/FM
SELECT
GAIN
CONTROL
VOLTAGE
INPUT
POWER- POWER-
GAIN
1.23V DOWN 2 DOWN 1
CONTROL REFERENCE
VOLTAGE OUTPUT
REFERENCE
INPUT
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000







AD6121 pdf, 数据表
AD6121
50.00
40.00
30.00
TA = 40؇C
TA = +85؇C
TA = +25؇C
20.00
10.00
0.00
0
50 100 150 200 250 300
FREQUENCY MHz
Figure 14. IF Amplifier Maximum Gain vs. Frequency,
TA = –40°C, +25°C and +85°C
60.00
40.00
VGAIN = +2.5V
20.00
0.00
20.00
VGAIN = +1.5V
40.00
VGAIN = +0.5V
60.00
0
100 200
FREQUENCY MHz
300
Figure 15. IF Amplifier Gain vs. Frequency, VGAIN =
+0.5 V, +1.5 V and = +2.5 V
10
20
30
40
50
60
0.5
1 1.5 2
VGAIN V
2.5
Figure 17. IF Amplifier Input 1 dB Compression Point vs.
VGAIN, IF = 85.38 MHz
6
TA = 40؇C
5 TA = +25؇C
4
TA = +85؇C
3
2
1
0
0 5 10 15
BASEBAND FREQUENCY MHz
Figure 18. Demodulator I Channel Gain vs. Baseband
Frequency, IF = 85 MHz
40.00
42.00
44.00
46.00
48.00
50.00
52.00
54.00
56.00
58.00
60.00
0
50 100 150 200 250 300
FREQUENCY MHz
Figure 16. IF Amplifier 1 dB Compression Point vs. Fre-
quency, VGAIN = +2.5 V
20
10
TA = 40؇C
TA = +25؇C
TA = +85؇C
0
10
20
0
100 200 300
INTERMEDIATE FREQUENCY MHz
400
Figure 19. Demodulator I Channel Gain vs. IF, Baseband
Frequency = 1 MHz, TA = –40°C, +25°C and +85°C
–8– REV. B







AD6121 equivalent, schematic
AD6121
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Shrink Small Outline Package (SSOP)
(RS-28)
0.407 (10.34)
0.397 (10.08)
28
0.311 (7.9)
0.301 (7.64)
1
15
0.212 (5.38)
0.205 (5.21)
14
0.078 (1.98) PIN 1
0.068 (1.73)
0.07 (1.79)
0.066 (1.67)
0.008 (0.203)
0.0256
(0.65)
0.002 (0.050) BSC
0.015 (0.38)
0.010 (0.25)
SEATING
PLANE
8
0
0.009 (0.229)
0.005 (0.127)
0.03 (0.762)
0.022 (0.558)
32-Leadless Chip Scale Package (LPCC)
(CP-32)
0.010
(0.25)
REF
0.205 (5.20)
0.197 (5.00) SQ
0.189 (4.80)
0.128 (3.25)
0.106 (2.70) SQ
0.049 (1.25)
25 32 PIN 1
24 1 INDICATOR
BOTTOM
VIEW
0.015 (0.38)
0.012 (0.30)
0.009 (0.23)
17
16
8
9
0.138 (3.50) BSC
0.018 (0.45)
0.016 (0.40)
0.014 (0.35)
0.020 (0.50)
BSC
0.039 (1.00)
0.035 (0.90)
0.031 (0.80)
0.002 (0.05)
0.001 (0.02)
0.000 (0.00)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
DIMENSIONS MEET JEDEC MO-220-VHHD-2
–16–
REV. B










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