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PDF ( 数据手册 , 数据表 ) AD9224

零件编号 AD9224
描述 Complete 12-Bit 40 MSPS Monolithic A/D Converter
制造商 Analog Devices
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AD9224 数据手册, 描述, 功能
a
FEATURES
Monolithic 12-Bit, 40 MSPS A/D Converter
Low Power Dissipation: 415 mW
Single +5 V Supply
No Missing Codes Guaranteed
Differential Nonlinearity Error: ؎0.33 LSB
Complete On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio: 68.3 dB
Spurious-Free Dynamic Range: 81 dB
Out-of-Range Indicator
Straight Binary Output Data
28-Lead SSOP Package
Compatible with 3 V Logic
Complete 12-Bit, 40 MSPS
Monolithic A/D Converter
AD9224
FUNCTIONAL BLOCK DIAGRAM
CLK
AVDD
DRVDD
VINA
VINB
SHA
MDAC1
GAIN = 16
MDAC2
GAIN = 4
MDAC3
GAIN = 4
CML
5
A/D
3
A/D
3
A/D
A/D
CAPT 5 3 3 4
CAPB
DIGITAL CORRECTION LOGIC
VREF
12
OUTPUT BUFFERS
OTR
SENSE
MODE
SELECT
1V
AD9224
BIT 1
(MSB)
BIT 12
(LSB)
REFCOM
AVSS DRVSS
PRODUCT DESCRIPTION
The AD9224 is a monolithic, single supply, 12-bit, 40 MSPS,
analog-to-digital converter with an on-chip, high performance
sample-and-hold amplifier and voltage reference. The AD9224
uses a multistage differential pipelined architecture with output
error correction logic to provide 12-bit accuracy at 40 MSPS
data rates, and guarantees no missing codes over the full operat-
ing temperature range.
The AD9224 combines a low cost high speed CMOS process
and a novel architecture to achieve the resolution and speed of
existing bipolar implementations at a fraction of the power
consumption and cost.
The input of the AD9224 allows for easy interfacing to both
imaging and communications systems. With a truly differential
input structure, the user can select a variety of input ranges and
offsets, including single-ended applications. The dynamic per-
formance is excellent.
The sample-and-hold (SHA) amplifier is well suited for both
multiplexed systems that switch full-scale voltage levels in suc-
cessive channels and sampling single-channel inputs at frequen-
cies up to and well beyond the Nyquist rate.
The AD9224’s wideband input, combined with the power and
cost savings over previously available monolithics, is suitable for
applications in communications, imaging and medical ultrasound.
The AD9224 has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy
and temperature drift requirements of the application.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range signal indicates an overflow
condition which can be used with the most significant bit to
determine low or high overflow.
PRODUCT HIGHLIGHTS
The AD9224 is fabricated on a very cost effective CMOS
process. High speed precision analog circuits are now combined
with high density logic circuits.
The AD9224 offers a complete single-chip sampling 12-bit,
40 MSPS analog-to-digital conversion function in 28-lead
SSOP package.
Low Power—The AD9224 at 415 mW consumes a fraction of
the power of presently available in existing monolithic solutions.
On-Board Sample-and-Hold (SHA)—The versatile SHA
input can be configured for either single-ended or differential
inputs.
Out of Range (OTR)—The OTR output bit indicates when
the input signal is beyond the AD9224’s input range.
Single Supply—The AD9224 uses a single +5 V power supply
simplifying system power supply design. It also features a sepa-
rate digital driver supply line to accommodate 3 V and 5 V logic
families.
Pin Compatibility—The AD9224 is pin compatible with the
AD9220, AD9221, AD9223 and AD9225 ADCs.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999







AD9224 pdf, 数据表
AD9224
INTRODUCTION
The AD9224 is a high performance, complete single-supply 12-
bit ADC. The analog input range of the AD9224 is highly flex-
ible allowing for both single-ended or differential inputs of
varying amplitudes that can be ac or dc coupled.
It utilizes a four-stage pipeline architecture with a wideband
input sample-and-hold amplifier (SHA) implemented on a cost-
effective CMOS process. Each stage of the pipeline, excluding
the last stage, consists of a low resolution flash A/D connected
to a switched capacitor DAC and interstage residue amplifier
(MDAC). The residue amplifier amplifies the difference be-
tween the reconstructed DAC output and the flash input for the
next stage in the pipeline. One bit of redundancy is used in each
of the stages to facilitate digital correction of flash errors. The
last stage simply consists of a flash A/D.
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. This means that while the
converter is capable of capturing a new input sample every clock
cycle, it actually takes three clock cycles for the conversion to be
fully processed and appear at the output. This latency is not a
concern in most applications. The digital output, together with
the out-of-range indicator (OTR), is latched into an output
buffer to drive the output pins. The output drivers of the
AD9224 can be configured to interface with +5 V or +3.3 V
logic families.
The AD9224 uses both edges of the clock in its internal timing
circuitry (see Figure 1 and specification page for exact timing
requirements). The A/D samples the analog input on the rising
edge of the clock input. During the clock low time (between the
falling edge and rising edge of the clock), the input SHA is in
the sample mode; during the clock high time it is in hold. Sys-
tem disturbances just prior to the rising edge of the clock and/or
excessive clock jitter may cause the input SHA to acquire the
wrong value, and should be minimized.
ANALOG INPUT AND REFERENCE OVERVIEW
Figure 13 is a simplified model of the AD9224. It highlights the
relationship between the analog inputs, VINA, VINB, and the
reference voltage, VREF. Like the voltage applied to the top of
the resistor ladder in a flash A/D converter, the value VREF
defines the maximum input voltage to the A/D core. The mini-
mum input voltage to the A/D core is automatically defined to
be –VREF.
VINA
AD9224
+VREF
VCORE
A/D
CORE
12
VINB
–VREF
Figure 13. Equivalent Functional Input Circuit
The addition of a differential input structure gives the user an
additional level of flexibility that is not possible with traditional
flash converters. The input stage allows the user to easily config-
ure the inputs for either single-ended operation or differential
operation. The A/D’s input structure allows the dc offset of the
input signal to be varied independently of the input span of the
converter. Specifically, the input to the A/D core is the differ-
ence of the voltages applied at the VINA and VINB input pins.
Therefore, the equation,
VCORE = VINA VINB
(1)
defines the output of the differential input stage and provides
the input to the A/D core.
The voltage, VCORE, must satisfy the condition,
VREF VCORE VREF
where VREF is the voltage at the VREF pin.
(2)
While an infinite combination of VINA and VINB inputs exist
that satisfy Equation 2, an additional limitation is placed on the
inputs by the power supply voltages of the AD9224. The power
supplies bound the valid operating range for VINA and VINB.
The condition,
AVSS – 0.3 V < VINA < AVDD + 0.3 V
AVSS – 0.3 V < VINB < AVDD + 0.3 V
(3)
where AVSS is nominally 0 V and AVDD is nominally +5 V,
defines this requirement. The range of valid inputs for VINA
and VINB is any combination that satisfies both Equations 2
and 3.
For additional information showing the relationship between
VINA, VINB, VREF and the digital output of the AD9224, see
Table IV.
Refer to Table I and Table II at the end of this section for a
summary of both the various analog input and reference
configurations.
ANALOG INPUT OPERATION
Figure 14 shows the equivalent analog input of the AD9224
which consists of a differential sample-and-hold amplifier
(SHA). The differential input structure of the SHA is highly
flexible, allowing the devices to be easily configured for either a
differential or single-ended input. The dc offset, or common-
mode voltage, of the input(s) can be set to accommodate either
single-supply or dual-supply systems. Note also, that the analog
inputs, VINA and VINB, are interchangeable, with the excep-
tion that reversing the inputs to the VINA and VINB pins re-
sults in a polarity inversion.
VINA
VINB
CPIN+
CPAR
QS1
CPIN
CPAR
QS1
CS
QH1 CS
CH
QS2
QS2
CH
Figure 14. Simplified Input Circuit
The AD9224 has a wide input range. The input peaks may be
moved to AVDD or AVSS before performance is compromised.
This allows for much greater flexibility when selecting single-
ended drive schemes. Op amps and ac coupling clamps can be
set to available reference levels rather than be dictated by what
the ADC “needs.”
–8– REV. A







AD9224 equivalent, schematic
AD9224
REFERENCE CONFIGURATIONS
The figures associated with this section on internal and external
reference operation do not show recommended matching series
resistors for VINA and VINB for the purpose of simplicity.
Please refer to the Driving the Analog Inputs section for a dis-
cussion of this topic. Also, the figures do not show the decou-
pling network associated with the CAPT and CAPB pins.
Please refer to the Reference Operation section for a discussion
of the internal reference circuitry and the recommended decou-
pling network shown in Figure 17.
USING THE INTERNAL REFERENCE
Single-Ended Input with 0 to 2 ؋ VREF Range
Figure 26a shows how to connect the AD9224 for a 0 V to 2 V
or 0 V to 4 V input range via pin strapping the SENSE pin. An
intermediate input range of 0 to 2 × VREF can be established
using the resistor programmable configuration in Figure 28.
In either case, both the midscale voltage and input span are
directly dependent on the value of VREF. More specifically, the
midscale voltage is equal to VREF while the input span is equal
to 2 × VREF. Thus, the valid input range extends from 0 to 2 ×
VREF. When VINA is 0 V, the digital output will be 000 Hex;
when VINA is 2 × VREF, the digital output will be FFF Hex.
Shorting the VREF pin directly to the SENSE pin places the
internal reference amplifier in unity-gain mode and the resultant
VREF output is 1 V. Therefore, the valid input range is 0 V to
2 V. However, shorting the SENSE pin directly to the REFCOM
pin configures the internal reference amplifier for a gain of 2.0
and the resultant VREF output is 2.0 V. Thus, the valid input
range becomes 0 V to 4 V. The VREF pin should be bypassed to
the REFCOM pin with a 10 µF tantalum capacitor in parallel
with a low-inductance 0.1 µF ceramic capacitor.
2 ؋ VREF
0V
10F 0.1F
SHORT FOR 0V TO 2V
INPUT SPAN
SHORT FOR 0V TO 4V
INPUT SPAN
VINA
VINB
VREF
AD9224
SENSE
REFCOM
Figure 26a. Internal Reference—2 V p-p Input Span,
VCM = 1 V, or 4 V p-p Input Span
Figure 26b illustrates the relation between reference voltage and
THD. Note that optimal performance occurs when the refer-
ence voltage is set to 1.5 V (input span = 3 V).
–60
–65
–70
–75
–80
–85
–90
1.0
1.2 1.4 1.6 1.8 2.0
REFERENCE VOLTAGE – V
2.2
Figure 26b. THD vs. Reference Voltage, FS = 40 MHz,
FIN = 10 MHz (Differential)
Figure 27 shows the single-ended configuration that gives good
dynamic performance (SINAD, SFDR). To optimize dynamic
specifications, center the common-mode voltage of the analog
input at approximately by 2.5 V by connecting VINB to a low
impedance 2.5 V source. As described above, shorting the
VREF pin directly to the SENSE pin results in a 1 V reference
voltage and a 2 V p-p input span. The valid range for input
signals is 1.5 V to 3.5 V. The VREF pin should be bypassed to
the REFCOM pin with a 10 µF tantalum capacitor in parallel
with a low-inductance 0.1 µF ceramic capacitor.
This reference configuration could also be used for a differential
input in which VINA and VINB are driven via a transformer as
shown in Figure 24. In this case, the common-mode voltage,
VCM, is set at midsupply by connecting the transformer’s center
tap to CML of the AD9224. VREF can be configured for 1.0 V or
2.0 V by connecting SENSE to either VREF or REFCOM re-
spectively. Note that the valid input range for each of the
differential inputs is one half of the single-ended input and thus
becomes VCM – VREF/2 to VCM + VREF/2.
3.5V
1.5V
10F
VINA
VCM AD9224
VINB
1V
VREF
0.1F
SENSE
REFCOM
Figure 27. Internal Reference—2 V p-p Input Span,
VCM = 2.5 V
–16–
REV. A










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