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PDF ( 数据手册 , 数据表 ) AD9221

零件编号 AD9221
描述 Monolithic A/D Converters
制造商 Analog Devices
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AD9221 数据手册, 描述, 功能
Complete 12-Bit 1.5/3.0/10.0 MSPS
Monolithic A/D Converters
AD9221/AD9223/AD9220
FEATURES
Monolithic 12-Bit A/D Converter Product Family
Family Members Are: AD9221, AD9223, and AD9220
Flexible Sampling Rates: 1.5 MSPS, 3.0 MSPS, and
10.0 MSPS
Low Power Dissipation: 59 mW, 100 mW, and 250 mW
Single 5 V Supply
Integral Nonlinearity Error: 0.5 LSB
Differential Nonlinearity Error: 0.3 LSB
Input Referred Noise: 0.09 LSB
Complete On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio: 70 dB
Spurious-Free Dynamic Range: 86 dB
Out-of-Range Indicator
Straight Binary Output Data
28-Lead SOIC and 28-Lead SSOP
GENERAL DESCRIPTION
The AD9221, AD9223, and AD9220 are a generation of high
performance, single supply 12-bit analog-to-digital converters.
Each device exhibits true 12-bit linearity and temperature drift
performance1 as well as 11.5-bit or better ac performance.2 The
AD9221/AD9223/AD9220 share the same interface options,
package, and pinout. Thus, the product family provides an upward
or downward component selection path based on performance,
sample rate and power. The devices differ with respect to their
specified sampling rate, and power consumption, which is reflected
in their dynamic performance over frequency.
The AD9221/AD9223/AD9220 combine a low cost, high speed
CMOS process and a novel architecture to achieve the resolution
and speed of existing hybrid and monolithic implementations at
a fraction of the power consumption and cost. Each device is a
complete, monolithic ADC with an on-chip, high performance,
low noise sample-and-hold amplifier and programmable voltage
reference. An external reference can also be chosen to suit the
dc accuracy and temperature drift requirements of the application.
The devices use a multistage differential pipelined architecture
with digital output error correction logic to provide 12-bit accu-
racy at the specified data rates and to guarantee no missing
codes over the full operating temperature range.
The input of the AD9221/AD9223/AD9220 is highly flexible,
allowing for easy interfacing to imaging, communications, medi-
cal, and data-acquisition systems. A truly differential input
structure allows for both single-ended and differential input
interfaces of varying input spans. The sample-and-hold
NOTES
1Excluding internal voltage reference.
2Depends on the analog input configuration.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
FUNCTIONAL BLOCK DIAGRAM
CLK
AVDD
DVDD
VINA
VINB
CAPT
CAPB
VREF
SENSE
SHA
MDAC1
GAIN = 16
MDAC2
GAIN = 8
MDAC3
GAIN = 4
5
A/D
4
A/D
3
A/D
54
3
DIGITAL CORRECTION LOGIC
12
OUTPUT BUFFERS
A/D
3
MODE
SELECT
1V
AD9221/AD9223/AD9220
REFCOM
AVSS
DVSS
CML
OTR
BIT 1
(MSB)
BIT 12
(LSB)
amplifier (SHA) is equally suited for both multiplexed sys-
tems that switch full-scale voltage levels in successive channels
as well as sampling single-channel inputs at frequencies up to
and beyond the Nyquist rate. Also, the AD9221/AD9223/AD9220
is well suited for communication systems employing Direct-
IF down conversion since the SHA in the differential input
mode can achieve excellent dynamic performance far beyond its
specified Nyquist frequency.2
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an over-
flow condition that can be used with the most significant bit to
determine low or high overflow.
PRODUCT HIGHLIGHTS
The AD9221/AD9223/AD9220 family offers a complete single-
chip sampling 12-bit, analog-to-digital conversion function in
pin compatible 28-lead SOIC and SSOP packages.
Flexible Sampling Rates—The AD9221, AD9223, and AD9220
offer sampling rates of 1.5 MSPS, 3.0 MSPS, and 10.0 MSPS,
respectively.
Low Power and Single Supply—The AD9221, AD9223, and
AD9220 consume only 59 mW, 100 mW, and 250 mW, respec-
tively, on a single 5 V power supply.
Excellent DC Performance Over Temperature—The AD9221/
AD9223/AD9220 provide 12-bit linearity and temperature drift
performance.1
Excellent AC Performance and Low Noise—The AD9221/
AD9223/AD9220 provide better than 11.3 ENOB performance
and have an input referred noise of 0.09 LSB rms.2
Flexible Analog Input Range—The versatile on-board sample-
and-hold (SHA) can be configured for either single-ended or
differential inputs of varying input spans.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.







AD9221 pdf, 数据表
AD9221/AD9223/AD9220
AD9220–Typical Performance Characteristics (AVDD = 5 V, DVDD = 5 V, fSAMPLE = 10 MSPS, TA = 25؇C)
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
1
CODE
4095
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
1
CODE
4095
8,123,672
134,613
130,323
N–1 N
N+1
CODE
TPC 19. Typical DNL
TPC 20. Typical INL
TPC 21. “Grounded-Input”
Histogram (Input Span = 2 V p-p)
80
75
70
65
60
55
50
45
40
0.1
–0.5dB
–6dB
–20dB
1.0 10.0
FREQUENCY – MHz
TPC 22. SINAD vs. Input Frequency
(Input Span = 2.0 V p-p, VCM = 2.5 V)
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
0.5
–20dB
–6dB
–0.5dB
1.0
FREQUENCY – MHz
10.0
TPC 23. THD vs. Input Frequency
(Input Span = 2.0 V p-p, VCM = 2.5 V)
80
75
–0.5dB
70 –6.0dB
65
60
55 –20.0dB
50
45
40
0.1
1.0
FREQUENCY – MHz
10.0
TPC 24. SINAD vs. Input Frequency
(Input Span = 5.0 V p-p, VCM = 2.5 V)
–50
–55
–60
–65
–70
–75
–80
–85
–90
0.1
–20.0dB
–0.5dB
–6.0dB
1.0
FREQUENCY – MHz
10.0
TPC 25. THD vs. Input Frequency
(Input Span = 5.0 V p-p, VCM = 2.5 V)
–60
–65
–70
–75
–80
–85
–90
–95
–100
5V p-p
2V p-p
1 10
SAMPLE RATE – MSPS
15
TPC 26. THD vs. Clock Frequency
(AIN = –0.5 dB, fIN = 1.0 MHz,
VCM = 2.5 V)
90
80
SFDR
70
60
SNR
50
40
30
20
10
–60 –50 –40 –30 –20 –10
AIN – dBFS
0
TPC 27. SNR/SFDR vs. AIN (Input
Amplitude) (fIN = 5.0 MHz, Input
Span = 2 V p-p, VCM = 2.5 V)
–8– REV. E







AD9221 equivalent, schematic
AD9221/AD9223/AD9220
AC COUPLING AND INTERFACE ISSUES
For applications where ac coupling is appropriate, the op amp’s
output can be easily level shifted to the common-mode voltage,
VCM, of the AD9221/AD9223/AD9220 via a coupling capacitor.
This has the advantage of allowing the op amp’s common-mode
level to be symmetrically biased to its midsupply level (i.e.,
(VCC + VEE)/2). Op amps that operate symmetrically with respect
to their power supplies typically provide the best ac performance
as well as the greatest input/output span. Thus, various high
speed/performance amplifiers that are restricted to +5 V/–5 V
operation and/or specified for 5 V single-supply operation can be
easily configured for the 5 V or 2 V input span of the AD9221/
AD9223/AD9220. The best ac distortion performance is achieved
when the A/D is configured for a 2 V input span and common-
mode voltage of 2.5 V. Note that differential transformer coupling,
which is another form of ac coupling, should be considered for
optimum ac performance.
Simple AC Interface
Figure 15 shows a typical example of an ac-coupled, single-ended
configuration. The bias voltage shifts the bipolar, ground-refer-
enced input signal to approximately VREF. The value for C1
and C2 will depend on the size of the resistor, R. The capacitors,
C1 and C2, are typically a 0.1 µF ceramic and 10 µF tanta-
lum capacitor in parallel to achieve a low cutoff frequency
while maintaining a low impedance over a wide frequency
range. The combination of the capacitor and the resistor form a
high-pass filter with a high-pass –3 dB frequency determined
by the equation,
( )( )f3 dB = 1 / 2 × π × R × C1 + C2
The low impedance VREF voltage source both biases the VINB
input and provides the bias voltage for the VINA input. Figure 15
shows the VREF configured for 2.5 V; thus the input range
+VREF
0V
–VREF
VIN
+5V
–5V
C1
C2
RS
AD9221/
AD9223/
VINA AD9220
R
RS
VINB
C2 C1
VREF
SENSE
Figure 15. AC-Coupled Input
of the A/D is 0 V to 5 V. Other input ranges could be selected
by changing VREF, but the A/D’s distortion performance will
degrade slightly as the input common-mode voltage deviates
from its optimum level of 2.5 V.
Alternative AC Interface
Figure 16 shows a flexible ac-coupled circuit that can be config-
ured for different input spans. Since the common-mode voltage
of VINA and VINB are biased to midsupply independent of
VREF, VREF can be pin-strapped or reconfigured to achieve
input spans between 2 V and 5 V p-p. The AD9221/AD9223/
AD9220’s CMRR along with the symmetrical coupling R-C
networks will reject both power supply variations and noise. The
resistors, R, establish the common-mode voltage. They may
have a high value (e.g., 5 k) to minimize power consumption
and establish a low cutoff frequency. The capacitors, C1 and
C2, are typically 0.1 µF ceramic and 10 µF tantalum capacitors
in parallel to achieve a low cutoff frequency while maintaining a
low impedance over a wide frequency range. RS isolates the
buffer amplifier from the A/D input. The optimum performance
is achieved when VINA and VINB are driven via «Immetrical
networks. The f–3 dB point can be approximated by the equation,
( )( )f–3 dB = 1 / 2 × π × R / 2 × C1 + C2
+5V
VIN
+5V
C1
R
RS
VINA
–5V
+5V
C2 R
R
R
RS
C2 C1
AD9221/
AD9223/
AD9220
VINB
Figure 16. AC-Coupled Input-Flexible Input Span,
VCM = 2 V
Op Amp Selection Guide
Op amp selection for the AD9221/AD9223/AD9220 is highly
dependent on a particular application. In general, the performance
requirements of any given application can be characterized by
either time domain or frequency domain parameters. In either
case, one should carefully select an op amp that preserves the
performance of the A/D. This task becomes challenging when
one considers the AD9221/AD9223/AD9220’s high perfor-
mance capabilities coupled with other extraneous system level
requirements such as power consumption and cost.
The ability to select the optimal op amp may be further compli-
cated by either limited power supply availability and/or limited
acceptable supplies for a desired op amp. Newer, high perfor-
mance op amps typically have input and output range limitations
in accordance with their lower supply voltages. As a result, some
op amps will be more appropriate in systems where ac-coupling
is allowable. When dc-coupling is required, op amps without
headroom constraints, such as rail-to-rail op amps or ones
where larger supplies can be used, should be considered. The
following section describes some op amps currently available
from Analog Devices. The system designer is always encouraged
to contact the factory or local sales office to be updated on Analog
Devices’ latest amplifier product offerings. Highlights of the
areas where the op amps excel and where they may limit the
performance of the AD9221/AD9223/AD9220 is also included.
AD817:
50 MHz Unity GBW, 70 ns Settling to 0.01%, +5 V
to ± 15 V Supplies
Best Applications: Sample Rates < 7 MSPS, Low
Noise, 5 V p-p Input Range
Limits: THD above 100 kHz
AD826:
Dual Version of AD817
Best Applications: Differential and/or Low Imped-
ance Input
Drivers, Low Noise
Limits: THD above 100 kHz
AD818:
130 MHz @ G = +2 BW, 80 ns Settling to 0.01%,
+5 V to ± 15 V Supplies
Best Applications: Sample Rates < 7 MSPS, Low
Noise, 5 V p-p Input Range, Gains +2
Limits: THD above 100 kHz
–16–
REV. E










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