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PDF ( 数据手册 , 数据表 ) AD8150

零件编号 AD8150
描述 33 x 17/ 1.5 Gbps Digital Crosspoint Switch
制造商 Analog Devices
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AD8150 数据手册, 描述, 功能
FEATURES
Low cost
33 × 17, fully differential, nonblocking array
>1.5 Gbps per port NRZ data rate
Wide power supply range: +5 V, +3.3 V, −3.3 V, −5 V
Low power
400 mA (outputs enabled)
30 mA (outputs disabled)
PECL and ECL compatible
CMOS/TTL-level control inputs: 3 V to 5 V
Low jitter: <50 ps p-p
No heat sinks required
Drives a backplane directly
Programmable output current
Optimize termination impedance
User-controlled voltage at the load
Minimize power dissipation
Individual output disable for busing and building
Larger arrays
Double row latch
Buffered inputs
Available in 184-lead LQFP
APPLICATIONS
HD and SD digital video
Fiber optic network switching
GENERAL DESCRIPTION
AD8150 is a member of the Xstream line of products and is a
breakthrough in digital switching, offering a large switch array
(33 × 17) on very little power, typically less than 1.5 W.
Additionally, it operates at data rates in excess of 1.5 Gbps per
port, making it suitable for HDTV applications. Further, the
pricing of the AD8150 makes it affordable enough to be used
for SD applications. The AD8150 is also useful for OC-24
optical network switching.
The AD8150’s flexible supply voltages allow the user to operate
with either PECL or ECL data levels and will operate down to
3.3 V for further power reduction. The control interface is
CMOS/TTL compatible (3 V to 5 V).
Its fully differential signal path reduces jitter and crosstalk while
allowing the use of smaller single-ended voltage swings. The
AD8150 is offered in a 184-lead LQFP package that operates
over the industrial temperature range of 0°C to 85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
33 × 17, 1.5 Gbps Digital
Crosspoint Switch
AD8150
FUNCTIONAL BLOCK DIAGRAM
INP INN
CS
RE 33 33
7
D
A5
FIRST
RANK
17
7-BIT
LATCH
SECOND
RANK
17
7-BIT
LATCH
17
33 17
DIFFERENTIAL
SWITCH
MATRIX 17
OUTP
OUTN
WE
UPDATE
RESET
AD8150
Figure 1. Functional Block Diagram
500mV
100mV/
DIV
–500mV
100ps/DIV
Figure 2. Output Eye Pattern, 1.5 Gbps
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.







AD8150 pdf, 数据表
AD8150
Pin No.
131
133
134
136
137
140
141
143
144
146
147
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
173
174
176
177
179
180
182
183
Mnemonic
IN10N
IN11P
IN11N
IN12P
IN12N
IN13P
IN13N
IN14P
IN14N
IN15P
IN15N
VEEREF
REF
VSS
D6
D5
D4
D3
D2
D1
D0
A4
A3
A2
A1
A0
UPDATE
WE
RE
CS
RESET
VDD
IN16P
IN16N
IN17P
IN17N
IN18P
IN18N
IN19P
IN19N
Type
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
R-program
R-program
Power supply
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Power supply
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
Description
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
Connection Point for Output Logic Pull-Down Programming Resistor
(must be connected to VEE)
Connection Point for Output Logic Pull-Down Programming Resistor
Most Negative Control Logic Supply
Enable/DISABLE Output
(32) MSB Input Select
(16)
(8)
(4)
(2)
(1) LSB Input Select
(16) MSB Output Select
(8)
(4)
(2)
(1) LSB Output Select
Second-Rank Program
First-Rank Program
Enable Readback
Enable Chip to Accept Programming
Disable All Outputs (Hi-Z)
Most Positive Control Logic Supply
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
Rev. A | Page 8 of 44







AD8150 equivalent, schematic
AD8150
CS INPUT
UPDATE INPUT
ENABLING
OUT[0:16][N:P]
OUTPUTS
TOGGLE
OUT[0:16][N:P]
OUTPUTS
DISABLING
OUT[0:16][N:P]
OUTPUTS
DATA FROM RANK 1
PREVIOUS RANK 2 DATA
DATA FROM RANK 1
DATA FROM RANK 2
tCSU
tUOE
tUOD
tUOT
tUW
Figure 27. Second-Rank Update Cycle
tCHU
Table 7. Second-Rank Update Cycle
Symbol
tCSU Setup Time
tCHU Hold Time
tUOE Output Enable Times
tUOT Output Toggle Times
tUOD Output Disable Times
tUW Width of Update Pulse
Parameter
Chip select to update
Chip select from update
Update to output enable
Update to output reprogram
Update to output disabled
Conditions
TA = 25°C
VDD = 5 V
VCC = 5 V
Min Typ Max Unit
0 ns
0 ns
25 40
ns
25 40
ns
25 30
ns
15 ns
Rev. A | Page 16 of 44










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