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PDF ( 数据手册 , 数据表 ) AD808

零件编号 AD808
描述 Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming
制造商 Analog Devices
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AD808 数据手册, 描述, 功能
a Fiber Optic Receiver with Quantizer and
Clock Recovery and Data Retiming
AD808
FEATURES
Meets CCITT G.958 Requirements
for STM-4 Regenerator—Type A
Meets Bellcore TR-NWT-000253 Requirements for OC-12
Output Jitter: 2.5 Degrees RMS
622 Mbps Clock Recovery and Data Retiming
Accepts NRZ Data, No Preamble Required
Phase-Locked Loop Type Clock Recovery—
No Crystal Required
Quantizer Sensitivity: 4 mV
Level Detect Range: 10 mV to 40 mV, Programmable
Single Supply Operation: +5 V or –5.2 V
Low Power: 400 mW
10 KH ECL/PECL Compatible Output
Package: 16-Lead Narrow 150 mil SOIC
PRODUCT DESCRIPTION
The AD808 provides the receiver functions of data quantiza-
tion, signal level detect, clock recovery and data retiming for
622 Mbps NRZ data. The device, together with a PIN
diode/preamplifier combination, can be used for a highly inte-
grated, low cost, low power SONET OC-12 or SDH STM-4
fiber optic receiver.
The receiver front end signal level detect circuit indicates when
the input signal level has fallen below a user adjustable thresh-
old. The threshold is set with a single external resistor. The
signal level detect circuit 3 dB optical hysteresis prevents chatter
at the signal level detect output.
The PLL has a factory trimmed VCO center frequency and a
frequency acquisition control loop that combine to guarantee
frequency acquisition without false lock. This eliminates a reli-
ance on external components such as a crystal or a SAW filter,
to aid frequency acquisition.
The AD808 acquires frequency and phase lock on input data
using two control loops that work without requiring external
control. The frequency acquisition control loop initially acquires
the frequency of the input data, acquiring frequency lock on
random or scrambled data without the need for a preamble. At
frequency lock, the frequency error is zero and the frequency
detector has no further effect. The phase acquisition control
loop then works to ensure that the output phase tracks the input
phase. A patented phase detector has virtually eliminated pat-
tern jitter throughout the AD808.
The device VCO uses a ring oscillator architecture and patented
low noise design techniques. Jitter is 2.5 degrees rms. This low
jitter results from using a fully differential signal architecture,
Power Supply Rejection Ratio circuitry and a dielectrically
isolated process that provides immunity from extraneous signals
on the IC. The device can withstand hundreds of millivolts of
power supply noise without an effect on jitter performance.
The user sets the jitter peaking and acquisition time of the PLL
by choosing a damping factor capacitor whose value determines
loop damping. CCITT G.958 Type A jitter transfer require-
ments can easily be met with a damping factor of 5 or greater.
Device design guarantees that the clock output frequency will
drift by less than 20% in the absence of input data transitions.
Shorting the damping factor capacitor, CD, brings the clock
output frequency to the VCO center frequency.
The AD808 consumes 400 mW and operates from a single
power supply at either +5 V or –5.2 V.
FUNCTIONAL BLOCK DIAGRAM
QUANTIZER
PIN
NIN
THRADJ
SIGNAL
LEVEL
DETECTOR
LEVEL
DETECT
COMPARATOR/
BUFFER
CF1 CF2
DET
COMPENSATING
ZERO
PHASE-LOCKED LOOP
FDET
AD808
RETIMING
DEVICE
LOOP
FILTER
VCO
CLKOUTP
CLKOUTN
DATAOUTP
DATAOUTN
SDOUT
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998







AD808 pdf, 数据表
AD808
Center Frequency Clamp (Figure 13)
An N-channel FET circuit can be used to bring the AD808
VCO center frequency to within ± 10% of 622 MHz when
SDOUT indicates a Loss of Signal (LOS). This effectively re-
duces the frequency acquisition time by reducing the frequency
error between the VCO frequency and the input data frequency
at clamp release. The N-FET can have “on” resistance as high
as 1 kand still attain effective clamping. However, the chosen
N-FET should have greater than 10 M“off” resistance and
less than 100 nA leakage current (source and drain) so as not to
alter normal PLL performance.
N_FET
CD
1 DATAOUTN
2 DATAOUTP
3 VCC2
4 CLKOUTN
VEE 16
SDOUT 15
AVCC2 14
PIN 13
5 CLKOUTP
NIN 12
6 VCC1
7 CF1
AVCC1 11
THRADJ 10
8 CF2 AD808 AVEE 9
Figure 13. Center Frequency Clamp Schematic
CD
0.047
0.10
0.47
PEAK
0.11
0.07
0.04
DIV
20.00m
RBW:
DIV
36.00m
START
STOP
30Hz ST: 3.07 min RANGE: R=
500.000Hz
100 000.000Hz
0, T=
0dBm
Figure14. Jitter Transfer vs. CD
C1 0.1F
R1 R2
100100
J1 C3 0.1F
DATAOUTN
DATAOUTP
J2 C4 0.1F
J3 C5 0.1F
CLKOUTN
CLKOUTP
J4
C6
0.1F
R3
100
R4
100
C2
0.1F
R9
154
R5 100
R6 100
R10
154
1
2
R7 100
R8 100
C7
3
4
5
R11
154
C8 TP1
R12 CD
154TP2
6
7
8
50STRIP LINE
EQUAL LENGTH
DATAOUTN
VEE
DATAOUTP SDOUT
VCC2
AVCC2
CLKOUTN
PIN
CLKOUTP
NIN
VCC1
CF1
AVCC1
THRADJ
CF2 AD808 AVEE
TP7 TP8
16
15
14 C9
13
12
11
C10
10
RTHRESH
9
J5
SDOUT
C12
0.1F
R13
301
TP5
TP6
R14
49.9
R16 3.65k
R15
49.9C13 0.1F J6
PIN
NIN
C14 0.1F J7
VECTOR PINS SPACED FOR RN55C
TYPE RESISTOR; COMPONENT
SHOWN FOR REFERENCE ONLY
NOTE:
C11
TP3 10F TP4
+5V GND
NOTE: INTERCONNECT RUN
UNDER DUT
VECTOR PINS SPACED THROUGH-HOLE
CAPACITOR ON VECTOR CUPS; COMPONENT
SHOWN FOR REFERENCE ONLY
C7–C10 ARE 0.1µF BYPASS CAPACITORS
RIGHT ANGLE SMA CONNECTOR
OUTER SHELL TO GND PLANE
ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT
TPxo TEST POINTS ARE VECTORBOARD K24A/M PINS
Figure 15. Evaluation Board Schematic
–8– REV. 0














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