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PDF ( 数据手册 , 数据表 ) ADP1147AR-5

零件编号 ADP1147AR-5
描述 High Efficiency Step-Down Switching Regulator Controllers
制造商 Analog Devices
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ADP1147AR-5 数据手册, 描述, 功能
a
High Efficiency Step-Down
Switching Regulator Controllers
ADP1147-3.3/ADP1147-5
FEATURES
Greater Than 95% Efficiency
Current Mode Switching Architecture Provides
Superior Load and Line Transient Response
Wide Input Voltage Range 3.5 V* to 16 V
User Defined Current Limit
Short Circuit Protection
Shutdown Pin
Low Dropout Voltage
Low Standby Current 160 A typ
Low Cost
Available in 8-Lead PDIP or 8-Lead SOIC
APPLICATIONS
Portable Computers
Modems
Cellular Telephones
Portable Equipment
GPS Systems
Handheld Instruments
GENERAL DESCRIPTION
The ADP1147 is part of a family of High Efficiency Step-Down
Switching Regulators. These regulators offer superior load and
line transient response, a user defined current limit and an
automatic power savings mode. The automatic power savings
mode is used to maintain efficiency at lower output currents.
The ADP1147 incorporates a constant off-time, current mode
switching architecture to drive an external P-channel MOSFET
at frequencies up to 250 kHz. Constant off-time switching gen-
erates a constant ripple current in the external inductor. This
results in a wider input voltage operating range of 3.5 V* to
16 V, and a less complex circuit design.
*3.5 volt operation is for the ADP1147-3.3.
VIN (5.2V TO 12V)
+
1F
+ CIN
100F
P-CHANNEL
IRF7204
L*
50H
D1
30BQ040
RSENSE**
0.05
VOUT
5V/2A
+ COUT
390F
0V = NORMAL
1.5V = SHUTDOWN
VIN
P-DRIVE
CC RC
3300pF 1k
ADP1147
SHUTDOWN
ITH SENSE(+)
CT SENSE(–)
CT GND
470pF
1000pF
*COILTRONICS CTX 50–2MP
**KRL SL-1-C1-0R050J
SHUTDOWN
Figure 1. High Efficiency Step-Down Converter
(Typical Application)
FUNCTIONAL BLOCK DIAGRAM
VIN P-DRIVE GROUND SENSE(+) SENSE(–)
ADP1147
SLEEP
S VTH2
VTH1
1
QR
S
T
2
R
QS
V
B
C 10mV to 150mV
13k
G
VOS
1.25V
5pF
100k
OFF-TIME VIN
CONTROL SENSE(–)
REFERENCE
CT ITH SHUTDOWN
A very low dropout voltage with excellent output regulation can
be obtained by minimizing the dc resistance of the Inductor, the
RSENSE resistor, and the RDS(ON) of the P-MOSFET. The power
savings mode conserves power by reducing switching losses at
lower output currents. When the output load current falls below
the minimum required for the continuous mode the ADP1147
will automatically switch to the power savings mode. It will remain
in this mode until the inductor requires additional current or the
sleep mode is entered. In sleep mode with no load the standby
power consumption of the device is reduced to 2.0 mW typical
at VIN = 10 V.
For designs requiring even greater efficiencies refer to the
ADP1148 data sheet.
100
95 VIN = 6 VOLTS
90
VIN = 10 VOLTS
85
80
75
70
65
60
1 10 100 1k 10k
LOAD CURRENT – mA
Figure 2. ADP1147-5 Typical Efficiency, Figure 1 Circuit
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998







ADP1147AR-5 pdf, 数据表
ADP1147-3.3/ADP1147-5
The formula used to calculate the continuous operating fre-
quency is:
f = 1VVOIUNT++VVDD
tOFF
tOFF
= 1.3 × 104
× CT
×V REG
V OUT
VREG is the value of the desired output voltage. VOUT is the ac-
tual measured value of the output voltage. When in regulation
VREG/VOUT is equal to 1. The switching frequency of the ADP1147
decreases as the input voltage decreases. The ADP1147 will
reduce the tOFF time by increasing the discharge current in ca-
pacitor CT if the input to output voltage differential falls below
1.5 volts. This is to eliminate the possible occurrence of audible
switching prior to dropout.
Now that the operating frequency has been determined and the
value selected for CT, the required inductance for inductor L
can be computed. The inductor L should be chosen so it will
generate no more than 25 mV/RSENSE of peak-to-peak inductor
ripple current.
The following equation is used to determine the required value
for inductor L:
25 mV = (VOUT +V D ) × tOFF or
RSENSE
LMIN
LMIN
= (VOUT
+V D ) × tOFF
25 mV
× RSENSE
Substituting for tOFF above gives the minimum required induc-
tor value of:
LMIN = 5.1 × 105× RSENSE × CT × VREG
The ESR requirements for the output storage capacitor can be
relaxed by increasing the inductor value, but efficiency due to
copper losses will be reduced. Conversely, the use of too low an
inductance may allow the inductor current to become discon-
tinuous, causing the device to enter the power savings mode
prematurely. As a result of this the power savings threshold is
lowered and the efficiency at lower current levels is severely
reduced.
Inductor Core Considerations
Now that the minimum inductance value for L has been deter-
mined, the inductor core selection can be made. High efficiency
converters generally cannot afford the core losses found in low
cost powdered iron cores. This forces the use of a more expen-
sive ferrite, molypermalloy, or Kool Mu® cores. The typical
efficiency in Figure 1 reflects the use of a molypermalloy core.
The cost of the inductor can be cut in half by Using a Kool Mu
core type CTX 50-4 by Coiltronics, but the efficiency will be
approximately 1%–2% less. The actual core losses are not de-
pendent on the size of the core, but on the amount of induc-
tance. An increase in inductance will yield a decrease in the
amount of core loss. Although this appears to be desirable, more
inductance requires more turns of wire with added resistance
and greater copper losses.
Kool Mu is a registered trademark of Magnetics, Inc.
Using a ferrite cores in a design can produce very low core
losses, allowing the designer to focus on minimizing copper loss
and core saturation problems. Ferrite cores exhibit a condition
known as “Hard Saturation,” which results in an abrupt collapse
of the inductance when the peak design current is exceeded.
This causes the inductor ripple current to rise sharply, the out-
put ripple voltage to increase and the power savings mode of
operation to be erroneously activated. To prevent this from
occurring the core should never be allowed to saturate.
Molypermalloy (from Magnetics, Inc.) is a very good, low loss
core material for a toroids, but is more expensive than a ferrite
core. A reasonable compromise between price and performance,
from the same manufacturer is Kool Mu. Toroidal cores are
extremely desirable where efficient use of available space and
several layers of wire are required. They are available in various
surface mount configurations from Coiltronics Inc. and other
companies.
Power MOSFET Selection and Considerations
The ADP1147 requires the use of an external P-channel
MOSFET. The major parameters to be considered when select-
ing the power MOSFET are the threshold voltage VGS(TH) and
the on resistance of the device RDS(ON).
The minimum input voltage determines if the design requires a
logic level or a standard threshold MOSFET. In applications
where the input voltage is > 8 volts, a standard threshold
MOSFET with a VGS(TH) of < 4 volts can be used. In designs
where VIN is < 8 volts, a logic level MOSFET with a VGS(TH) of
< 2.5 volts is recommended. Note: If a logic level MOSFET
is selected, the supply voltage to the ADP1147 must not
exceed the absolute maximum for the VGS of the MOSFET
(e.g., < ± 8 volts for IRF7304).
The RDS(ON) requirement for the selected power MOSFET is
determined by the maximum output current (IMAX). An as-
sumption is made that when the ADP1147 is operating in the
continuous mode, either the Schottky Diode or the MOSFET
are always conducting the average load current. The following
formulas are used to determine the duty cycle of each of the
components.
P Channel MOSFET Duty Cycle =VOUT +V D
V IN +V D
Schottky Diode Duty Cycle = V IN V D
V IN +V D
Once the Duty Cycle is known, the RDS(ON) requirement for the
Power MOSFET can be determined by:
RDS(ON )
=
(V OUT
(V IN +V D ) × PP
+V D ) × I MAX 2 × (1+ δP
)
where PP is the max allowable power dissipation and where δP is
the temperature dependency of RDS(ON) for the MOSFET. Effi-
ciency and thermal requirements will determine the value of PP,
(refer to Efficiency section). MOSFETS usually specify the 1+ δ
as a normalized RDS(ON ) vs. temperature trace, and δ can be
approximated to 0.007/°C for most low voltage MOSFETs.
Output Diode Considerations
When selecting the output diode careful consideration should be
given to peak current and average power dissipation so the
maximum specifications for the diode are not exceeded.
–8– REV. 0














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