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PDF ( 数据手册 , 数据表 ) 160V

零件编号 160V
描述 In-System Programmable 3.3V Generic Digital CrosspointTM
制造商 Lattice Semiconductor
LOGO Lattice Semiconductor LOGO 


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160V 数据手册, 描述, 功能
ispGDXTM160V/VA
In-System Programmable
3.3V Generic Digital CrosspointTM
Features
Functional Block Diagram
• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
CROSSPOINT FAMILY
— Advanced Architecture Addresses Programmable
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
— “Any Input to Any Output” Routing
— Fixed HIGH or LOW Output Option for Jumper/DIP
Switch Emulation
— Space-Saving PQFP and BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
Test
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
I/O Pins D
ISP
Control
I/O
Cells
Global Routing
Pool
(GRP)
I/O
Cells
— 3.3V Core Power Supply
— 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay*
— 250MHz Maximum Clock Frequency*
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels (Individually Programmable)*
— Low-Power: 16.5mA Quiescent Icc*
— 24mA IOL Drive with Programmable Slew Rate
Control Option
— PCI Compatible Drive Capability*
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
Boundary
Scan
Control
Description
I/O Pins B
• ispGDXV™ OFFERS THE FOLLOWING ADVANTAGES
— 3.3V In-System Programmable Using Boundary Scan
Test Access Port (TAP)
— Change Interconnects in Seconds
The ispGDXV/VA architecture provides a family of fast,
flexible programmable devices to address a variety of
system-level digital signal routing and interface require-
ments including:
• FLEXIBLE ARCHITECTURE
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock/Clock Enable Input Pins (four) or
Programmable Clocks/Clock Enables from I/O Pins
(40)
— Single Level 4:1 Dynamic Path Selection (Tpd=3.5ns)
— Programmable Wide-MUX Cascade Feature
Supports up to 16:1 MUX
— Programmable Pull-ups, Bus Hold Latch and Open
Drain on I/O Pins
— Outputs Tri-state During Power-up (“Live Insertion”
Friendly)
• DESIGN SUPPORT THROUGH LATTICE’S ispGDX
DEVELOPMENT SOFTWARE
— MS Windows or NT / PC-Based or Sun O/S
— Easy Text-Based Design Entry
— Automatic Signal Routing
— Program up to 100 ISP Devices Concurrently
— Simulator Netlist Generation for Easy Board-Level
Simulation
• Multi-Port Multiprocessor Interfaces
• Wide Data and Address Bus Multiplexing
(e.g. 16:1 High-Speed Bus MUX)
• Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc.)
• Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The devices feature fast operation, with input-to-output
signal delays (Tpd) of 3.5ns and clock-to-output delays of
3.5ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Rout-
ing Pool (GRP). All I/O pin inputs enter the GRP directly
or are registered or latched so they can be routed to the
required I/O outputs. I/O pin inputs are defined as four
sets (A,B,C,D) which have access to the four MUX inputs
* “VA” Version Only
Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
July 2000
gdx160va_04
1







160V pdf, 数据表
Specifications ispGDX160VA
Absolute Maximum Ratings 1,2
Supply Voltage Vcc ................................. -0.5 to +5.4V
Input Voltage Applied ............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the Absolute Maximum Ratingsmay cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.
DC Recommended Operating Conditions
SYMBOL
VCC
VCCIO
PARAMETER
Supply Voltage
I/O Reference Voltage
Commercial
Industrial
TA = 0°C to +70°C
TA = -40°C to +85°C
Capacitance (TA=25oC, f=1.0 MHz)
MIN.
3.00
3.00
2.3
MAX. UNITS
3.60 V
3.60 V
3.60 V
Table 2-0005/gdx160va
SYMBOL
PARAMETER
C1 I/O Capacitance
C2 Dedicated Clock Capacitance
PACKAGE TYPE
PQFP
BGA, fpBGA
PQFP
BGA, fpBGA
TYPICAL
7
10
8
10
UNITS
pf
pf
pf
pf
TEST CONDITIONS
VCC = 3.3V, VI/O = 2.0V
VCC = 3.3V, VY= 2.0V
Table 2-0006/gdx160va
Erase/Reprogram Specifications
PARAMETER
Erase/Reprogram Cycles
MINIMUM
10,000
MAXIMUM
UNITS
Cycles
8







160V equivalent, schematic
Specifications ispGDX160V
Absolute Maximum Ratings 1,2
Supply Voltage Vcc ................................. -0.5 to +5.4V
Input Voltage Applied ............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the Absolute Maximum Ratingsmay cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.
DC Recommended Operating Conditions
SYMBOL
VCC
Supply Voltage
VIL1
Input Low Voltage
VIH1
Input High Voltage
1. Typical 100mV of input hysteresis.
PARAMETER
Commercial TA = 0°C to +70°C
Industrial
TA = -40°C to +85°C
MIN.
3.0
3.0
-0.3
2.0
MAX. UNITS
3.6 V
3.6 V
0.8 V
5.25 V
Table 2-0005/gdxv
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL
C1
C2
PARAMETER
I/O Capacitance
Dedicated Clock Capacitance
Erase/Reprogram Specifications
PARAMETER
Erase/Reprogram Cycles
TYPICAL
8
10
UNITS
pf
pf
TEST CONDITIONS
VCC = 3.3V, VI/O = 2.0V
VCC = 3.3V, VY= 2.0V
Table 2 - 0006
MINIMUM
10,000
MAXIMUM
UNITS
Cycles
16










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