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PDF ( 数据手册 , 数据表 ) ADV7173

零件编号 ADV7173
描述 Digital PAL/NTSC Video Encoder
制造商 Analog Devices
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ADV7173 数据手册, 描述, 功能
a
Digital PAL/NTSC Video Encoder
with Six DACs (10 Bits), Color Control
and Enhanced Power Management
ADV7172/ADV7173
FEATURES
ITU-R1 BT601/656 YCrCb to PAL/NTSC Video Encoder
Six High Quality 10-Bit Video DACs
SSAF™ (Super Sub-Alias Filter)
Advanced Power Management Features
PC’98-Compliant (TV Detect with Polling and Auto
Shutdown to Save On Power Consumption)
Low Power DAC Mode
Individual DAC ON/OFF Control
Variable DAC Output Current (5 mA–36 mA)
Ultralow Sleep Mode Current
Hue, Brightness, Contrast and Saturation Controls
CGMS (Copy Generation Management System)
WSS (Wide Screen Signalling)
NTSC-M, PAL-M/N, PAL-B/D/G/H/I, PAL-60
YUV Betacam, MII and SMPTE/EBU N10 Output Levels
Single 27 MHz Clock Required (؋2 Oversampling)
80 dB Video SNR
32-Bit Direct Digital Synthesizer for Color Subcarrier
Multistandard Video Output Support:
Composite (CVBS)
Component S-Video (Y/C)
Component YUV
EuroSCART RGB
Component YUV + CHROMA + LUMA + CVBS
EuroSCART Output RGB + CHROMA + LUMA + CVBS
Programmable Clamping Output Signal
Advanced Programmable Power-On Reset Sequencing
Video Input Data Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Format
SMPTE 170M NTSC-Compatible Composite Video
ITU-R BT.470 PAL-Compatible Composite Video
Luma Sharpness Control
Programmable Luma Filters (Low-Pass [PAL/NTSC],
Notch [PAL/NTSC], Extended [SSAF], CIF and QCIF)
Programmable Chroma Filters (Low-Pass [0.65 MHz,
1.0 MHz, 1.2 MHz and 2.0 MHz], CIF and QCIF)
Programmable VBI (Vertical Blanking Interval)
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
CCIR and Square Pixel Operation
Integrated Subcarrier Locking to External Video Source
NOTES
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Programmable Multimode Master/Slave Operation
Macrovision Antitaping Rev 7.1 (ADV7172 Only)2
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
On-Board Color Bar Generation
On-Board Voltage Reference
2-Wire Serial MPU Interface (I2C®-Compatible and Fast I2C)
Single Supply 5 V or 3.3 V Operation
Small 48-Lead LQFP Package
APPLICATIONS
High Performance DVD Playback Systems, Portable
Video Equipment including Digital Still Cameras and
Laptop PCs, Video Games, PC Video/Multimedia and
Digital Satellite/Cable Systems (Set-Top Boxes/IRD)
GENERAL DESCRIPTION
The ADV7172/ADV7173 is an integrated Digital Video
Encoder that converts digital CCIR-601 4:2:2 8-bit component
video data into a standard analog baseband television signal
compatible with worldwide standards.
There are six DACs available on the ADV7172/ADV7173. In
addition to the Composite output signal there is the facility to
output S-VHS Y/C Video, RGB Video and YUV Video.
The on-board SSAF (Super Sub-Alias Filter), with extended
luminance frequency response and sharp stopband attenuation,
enables studio quality video playback on modern TVs, giving
optimal horizontal line resolution. An additional sharpness control
feature allows extra luminance boost on the frequency response.
An advanced power management circuit enables optimal control
of power consumption in both normal operating modes and
power down or sleep modes. A PC’98-Compliant autodetect
feature has been added to allow the user to determine whether
or not the DACs are correctly terminated. If not, the ADV7172/
ADV7173 flags that they are not connected through the Status
bit and provides the option of automatically powering them
down, thereby reducing power consumption.
The ADV7172/ADV7173 also supports both PAL and NTSC
square pixel operation. The parts also incorporate WSS and
CGMS-A data control generation.
1ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
2The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest
Macrovision version available.
SSAF is a trademark of Analog Devices, Inc.
I2C is a registered trademark of Philips Corporation.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001







ADV7173 pdf, 数据表
ADV7172/ADV7173
SDATA
SCLOCK
t5
t3 t3
t6
t1
t2
t7
t4
Figure 1. MPU Port Timing Diagram
t8
CLOCK
CONTROL
I / PS
HSYNC,
FIELD/VSYNC,
BLANK
t9 t10
t12
CONTROL
O / PS
PIXEL INPUT
DATA
Cb
Y
Cr
Y
Cb Y
HSYNC,
FIELD/VSYNC,
BLANK,
CSO_HSO,
VSO, CLAMP
t11 t13
t14
Figure 2. Pixel and Control Data Timing Diagram
TTXREQ
CLOCK
t16
t17
TTX
t18
4 CLOCK
CYCLES
4 CLOCK
CYCLES
4 CLOCK
CYCLES
Figure 3. Teletext Timing Diagram
3 CLOCK
CYCLES
4 CLOCK
CYCLES
DAC Average Current Consumption
DAC D, E, F: The average current consumed by each DAC is the DAC output current as determined by RSET2/VREF (see Appendix 8).
DAC A, B, C: In normal power mode the average current consumed by each DAC is the DAC output current as determined by RSET1
(see Appendix 8).
In Low Power Mode the average current consumed by each DAC is approximately half the DAC output current as determined by RSET1.
Consult AN-551 for detailed information on ADV7172/ADV7173 power management.
–8– REV. B







ADV7173 equivalent, schematic
ADV7172/ADV7173
COMPOSITE
VIDEO
e.g., VCR
OR CABLE
LCC1
GLL
P19-P12
VIDEO
DECODER
ADV7185
H/LTRANSITION
COUNT START
LOW
14 BITS
128 13 RESERVED
4 BITS
RESERVED
0 21
CLOCK
GREEN/COMPOSITE/Y
SCRESET/RTC
BLUE/LUMA/U
P7P0
RED/CHROMA/V
GREEN/COMPOSITE/Y
HSYNC
BLUE/LUMA/U
FIELD/VSYNC
RED/CHROMA/V
ADV7172/ADV7173
FSCPLL INCREMENT1
SEQUENCE
BIT2
RESET
5 BITS
BIT3
RESERVED
RESERVED
0
RTC
TIME SLOT: 01
14
NOT USED IN
ADV7172/ADV7173
19
VALID INVALID
SAMPLE SAMPLE
8 / LLC
67 68
NOTES
1 FSC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7172/ADV7173 FSC DDS REGISTER IS FSC PLL INCREMENT BITS 21:0 PLUS BITS 0:9
OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE
ADV7172/ADV7173.
2 SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
3 RESET BIT
RESET ADV7172/ADV7173s DDS
Figure 22. RTC Timing and Connections
Mode 0 (CCIR–656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7172/ADV7173 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data.
All timing information is transmitted using a 4-byte Synchronization Pattern. A synchronization pattern is sent immediately before
and after each line during active picture and retrace. Mode 0 is illustrated in Figure 23. The HSYNC, FIELD/VSYNC, and BLANK
(if not used) pins should be tied high during this mode.
ANALOG
VIDEO
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LlNES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
EAV CODE
Y
C
r
Y
F
F
0
0
0
0
X
Y
8
0
1
0
8
0
1
0
4 CLOCK
0F FAAA
0F FBBB
ANCILLARY DATA
(HANC)
268 CLOCK
SAV CODE
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
C
b
Y
C
r
Y
C
b
Y
C
r
Y
C
b
4 CLOCK
1440 CLOCK
4 CLOCK
END OF ACTIVE
VIDEO LINE
280 CLOCK
4 CLOCK
1440 CLOCK
START OF ACTIVE
VIDEO LINE
Figure 23. Timing Mode 0 (Slave Mode)
–16–
REV. B










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