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PDF ( 数据手册 , 数据表 ) ADV7160

零件编号 ADV7160
描述 96-Bit/ 220 MHz True-Color Video RAM-DAC
制造商 Analog Devices
LOGO Analog Devices LOGO 


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ADV7160 数据手册, 描述, 功能
a
96-Bit, 220 MHz
True-Color Video RAM-DAC
ADV7160/ADV7162
FEATURES
96-Bit Pixel Port for 1600 × 1280 × 24 Screen Resolution
220 MHz, 24-Bit (30-Bit Gamma Corrected) True-Color
Triple 10-Bit “Gamma Correcting” D/A Converters
2% (max) DAC to DAC Color Matching
Triple 256 × 10 (256 x 30) Color Palette RAM
On-Board User Definable Cursor (64 × 64 × 2)
Three Color Overlay
Cursor Palette RAM
Fully Programmable On-Board PLL
RS-343A/RS-170 Compatible RGB Analog Outputs
Tri-Level SYNC Functionality
TTL Compatible Digital Inputs
Standard MPU I/O Interface
Programmable Pixel Port: 24-Bit, 16-Bit, 15-Bit &
8-Bit (Pseudo)
Pixel Data Serializer:
Multiplexed Pixel Input Ports; 2:1, 4:1, 8:1
+5 V CMOS Monolithic Construction
160-Lead Plastic Quad Flatpack (QFP): ADV7162
160-Lead “Thermally Enhanced” QFP (PQUAD): ADV7160
ADV is a registered trademark of Analog Devices, Inc.
MODES OF OPERATION
1600 × 1200 × 30/24-Bit Resolution @ 85 Hz Screen Refresh
1600 × 1200 × 16/15-Bit Resolution @ 85 Hz Screen Refresh
1600 × 1200 × 8-Bit Resolution @ 85 Hz Screen Refresh
APPLICATIONS
Windows Accelerators
High Resolution, True Color Graphics
Professional Color Prepress Imaging
Digital TV (HDTV, Digital Video)
SPEED GRADES
@ 220 MHz
@ 170 MHz
@ 140 MHz
GENERAL DESCRIPTION
The ADV7160/ADV7162® is a 96-bit pixel port Video RAM-
DAC with color enhanced triple 10-bit DACs. The device also
includes a PLL and 64 × 64 hardware cursor. The ADV7160/
ADV7162 is specifically designed for use in the graphics sub-
system of high performance, color graphics workstations and
windows accelerators.
(Continued on page 15)
FUNCTIONAL BLOCK DIAGRAM
VAA
TRISYNC
SYNC
BLANK
A
PIXEL
DATA
(P7-P0)
B
C
D
PALETTE
SELECTS
(PS0, PS1)
24
24
24
24
8
ODD/EVEN
LOADIN
P
I
X
E8
L
I8
N
P
U
T8
M
U
L
T
I
P2
L
E
X
E
R
COLOR
MODE
MATRIX
8
8
8
PIXEL
MASK
8
8
8
BYPASS COLOR
MODE MATRIX
3 x 256 COLOR PALETTE
RED 256 x 10
GREEN 256 x 10
BLUE 256 x 10
10
10
10
10
10
10
PS
FUNCTION
DECODE
LOGIC
64 x 64
CURSOR
GENERATOR
2
2
3 COLOR OVERLAY PALETTE
RED 3 x 10
GREEN 3 x 10
BLUE 3 x 10
10
10
10
2 COLOR CURSOR PALETTE
RED 3 x 10
GREEN 3 x 10
BLUE 3 x 10
10
10
10
LOADOUT
PRGCKOUT
SCKOUT
SCKIN
CLOCK
CLOCK
CLOCK CONTROL
CLOCK DIVIDE &
SYNCHRONIZATION
CIRCUITRY
÷32, ÷16, ÷8, ÷4
SELECTOR
ECL TO
CMOS
PLL
ADDRESS
REGISTER
(A10-A0)
10
CONTROL
REGISTERS
MODE
REGISTER
(MR1)
10
CURSOR
REGISTERS
TEST
REGISTERS
ID
REGISTER
STATUS
REGISTER
PIXEL MASK
REGISTER
REVISION
REGISTER
PLL
REGISTERS
COMMAND
REGISTERS
(CR1-CR5)
MPU PORT
BLANK AND
SYNC LOGIC
10
S
E
L
E 10
C
T
O
R
10
RED
DAC
GREEN
DAC
BLUE
DAC
ADV7160/
ADV7162
DATA TO
PALETTES
VOLTAGE
REFERENCE
CIRCUIT
30
RED
REGISTER
GREEN
REGISTER
BLUE
REGISTER
10 (8+2)
10
JTAG TEST
ACCESS PORT
SYNCOUT
IOR
IOG
IOB
VREF
RSET
COMP
TDO
REV. 0
PLLREF
C1 R/W CE C0
D9–D0
TMS TCK TDI GND
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703







ADV7160 pdf, 数据表
ADV7160/ADV7162
CLOCK
LOADOUT
t10
LOADIN
PIXEL
INPUT
DATA
ANALOG
OUTPUT
DATA
(IOR, IOG, IOB,
SYNCOUT)
AN ...
DN
AN+1 ...
DN+1
AN+2 ...
DN+2
DOIGUITTPAULTINPPIPUETLTINOEANALOG
AN–1 ... DN–1
AN ... DN
AN+1 ... DN+1
AN+2 ... DN+2
tPD
Figure 7. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (4:1 Multiplex Mode)
CLOCK
LOADOUT
τ
τ-t11
LOADIN
PIXEL
INPUT
DATA
ANALOG
OUTPUT
DATA
(IOR, IOG, IOB,
SYNCOUT)
AN ...
DN
AN+1 ...
DN+1
AN+2 ...
DN+2
DOIUGTITPAULTINPIPPUETLITNOEANALOG
AN–1 ... DN–1
tPD
AN ... DN
AN+1 ... DN+1
AN+2 ... DN+2
Figure 8. Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (4:1 Multiplex Mode)
–8– REV. 0







ADV7160 equivalent, schematic
ADV7160/ADV7162
Other pixel data signals latched into the device by LOADIN
include SYNC, BLANK, TRISYNC and PS0A-D – PS1A-D.
Internally, data is pipelined through the part by the differential
pixel clock inputs, CLOCK and CLOCK or by the internal
pixel clock generated by the PLL on-board. The LOADIN
control signal need only have a frequency synchronous relation-
ship to the pixel CLOCK (see “Pipeline Delay & On-Board
Calibration” section). A completely phase independent
LOADIN signal can be used with the ADV7160/ADV7162,
allowing the CLOCK to occur anywhere during the LOADIN
cycle.
Alternatively, the LOADOUT signal of the ADV7160/ADV7162
can be used. LOADOUT can be connected either directly or
indirectly to LOADIN. Its frequency is automatically set to the
correct LOADIN requirement.
SYNC, BLANK
The BLANK and SYNC video control signals drive the analog
outputs to the Blank and Sync levels respectively. These signals
are latched into the part on the rising edge of LOADIN. The
SYNC information is encoded onto the IOG analog signal
when Bit CR22 of Command Register 2 is set to “1,” the IOR
analog signal when Bit CR41 of Command Register 4 is set to
“1” and the IOB analog signal when Bit CR42 of Command
Register 4 is set to “1.” The SYNC input is ignored if CR22,
CR41 and CR42 are set to logic “0.”
SYNCOUT
In some applications where it is not permissible to encode
SYNC on green (IOG), blue (IOB), or red (IOR), SYNCOUT
can be used as a separate TTL digital SYNC output. This has
the advantage over an independent (of the ADV7160/ADV7162)
SYNC in that it does not necessitate knowing the absolute pipe-
line delay of the part. This allows complete independence
between LOADIN/Pixel Data and CLOCK. The SYNC input
is connected to the device as normal with Bit CR22 of Com-
mand Register 2, Bit CR41 of Command Register 4 and Bit
CR42 of Command Register 4 are set to “0” thereby preventing
SYNC from being encoded onto IOG, IOR and IOB. The out-
put signal generates a TTL SYNCOUT with correct pipeline
delay which is capable of directly driving the composite SYNC
signal of a computer monitor.
TRISYNC
This input is used to generate a HDTV Sync on any of the DAC
outputs. Bit CR17 of Command Register 1 is set to “1”, en-
abling TRISYNC. When TRISYNC is low, the analog output
which has Sync enabled goes to the tri-sync level.
PS0A-D–PS1A-D (Palette Priority Select Inputs)
These multifunctional TTL compatible inputs can be config-
ured for three separate functions. The eight PS inputs are mul-
tiplexed to provide two bits which are used to provide one of
three different functions. The function is selected by Bit CR14
and Bit CR15 of Command Register 1.
CR15
0
0
1
1
CR14
0
1
0
1
Color Mode
Palette Select Mode
Bypass Mode Control (ADV7160 Only)
Overlay Color Mode
Ignore PS Inputs
However, in 8:1 Mode, for 8-Bit Pseudo Color, the unused Blue
Pixel Inputs are used to provide 8 extra PS inputs. The bypass
mode is unavailable in this case.
Palette Select Mode
These pixel port select inputs effectively determine whether the
devices RGB analog outputs are turned-on or shut down. When
the analog outputs are shut down, IOR, IOG and IOB are
forced to 0 mA regardless of the state of the pixel and control
data inputs. This state is determined on a pixel by pixel basis as
the PS0–PS1 inputs are multiplexed in exactly the same format
as the pixel port color data. These controls allow for switching
between multiple palette devices. If the values of PS0 and PS1
match the values programmed into bits MR16 and MR17 of the
Mode Register, then the device is selected, if there is no match
the device is effectively shut down.
Bypass Mode Control (ADV7160 Only)
In this mode PS1 is used to switch between one of the color
modes through the Color Palette and one of the Palette Bypass
modes on a pixel by pixel basis. The color mode through the
palette is selected using Bits CR27–CR24 of Command Regis-
ter 2. The Bypass Color Mode is selected using Bits CR17 and
CR16 of Command Register 1. PS1 then switches between the
Palette Color Mode, and the Bypass Color Mode. The PS0 in-
put continues to act as an overlay input, allowing Overlay Color
1 to be displayed.
PS0 PS1 Color Mode
0 0 Palette Color Mode (CR27–CR24)
0 1 Bypass Color Mode (CR17–CR16)
1 x Overlay Color 1
This mode is not available if using the ADV7162.
Overlay Color Mode
In this mode, the PS inputs provide control for a three color
overlay. Whenever the value other than “00” is placed on the
overlay inputs, the corresponding overlay color is displayed.
When the overlay inputs contain “00” the color is specified by
the main pixel inputs.
CLOCK CONTROL CIRCUIT
The ADV7160/ADV7162 has an integrated Clock Control Cir-
cuit (Figure 16). This circuit is capable of both generating the
ADV7160/ADV7162’s internal clocking signals as well as exter-
nal graphics subsystem clocking signals. Total system synchro-
nization can be attained by using the parts output clocking
signals to drive the controlling graphics processor’s master clock
as well as the video frame buffers shift clock signals.
CLOCK, CLOCK Inputs
The Clock Control Circuit is driven by the pixel clock inputs,
CLOCK and CLOCK. These inputs can be driven by a differ-
ential ECL oscillator running from a +5 V supply.
–16–
REV. 0










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