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PDF ( 数据手册 , 数据表 ) ADV611

零件编号 ADV611
描述 Closed Circuit TV Digital Video Codec
制造商 Analog Devices
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ADV611 数据手册, 描述, 功能
a
Closed Circuit TV Digital
Video Codec
ADV611/ADV612
FEATURES
Programmable “Quality Box”
Industrial Temperature Range (ADV612)
Hardware Frame Rate Reduction
100% Bitstream Compatible with the ADV601 and
ADV601LC
Precise Compressed Bit Rate Control
Field Independent Compression
8-Bit Video Interface Supports CCIR-656 and Multi-
plexed Philips Formats
General Purpose 16- or 32-Bit Host Interface with
512 Deep 32-Bit FIFO
PERFORMANCE
Real-Time Compression or Decompression of CCIR-601
to Video:
720 ؋ 288 @ 50 Fields/Sec — PAL
720 ؋ 243 @ 60 Fields/Sec — NTSC
Compression Ratios from Visually Loss-Less to 7500:1
Visually Loss-Less Compression At 4:1 on Natural
Images (Typical)
APPLICATIONS
CCTV Cameras and Systems
Time-Lapse Video Tape Recorders
Time-Lapse Video Disk Recorders
Wireless CCTV Cameras
Fiber CCTV Systems
GENERAL DESCRIPTION
The ADV611/ADV612 are low cost, single chip, dedicated func-
tion, all-digital-CMOS-VLSI devices capable of supporting
visually loss-less to 7500:1 real-time compression and decom-
pression of CCIR-601 digital video at very high image quality
levels. The chips integrate glueless video and host interfaces
with on-chip SRAM to permit low part count, system level
implementations suitable for a broad range of applications.
The ADV611/ADV612 are 100% bitstream compatible with
the ADV601. The ADV611/ADV612 comes in a 120-lead
LQFP package.
The ADV611/ADV612 are video encoders/decoders optimized
for closed circuit TV (CCTV) applications. With the ADV611/
ADV612, you can define a portion of each video field to be at a
higher quality level relative to the rest of the field. This “quality
box” feature significantly increases compression of less impor-
tant background details, while retaining the image’s overall
context. Additionally, the unique subband coding architecture
of the ADV611/ADV612 offer many application-specific
advantages. A review of the General Theory of Operation and
Applying the ADV611/ADV612 sections will help you get the
most use out of the ADV611/ADV612 in any given application.
The ADV611/ADV612 accept component digital video through
the Video Interface and outputs a compressed bitstream though the
Host Interface in Encode Mode. While in Decode Mode, the
ADV611/ADV612 accept compressed bitstream through the Host
Interface and outputs component digital video through the Video
Interface. The host accesses all of the ADV611/ADV612’s control
and status registers using the Host Interface. Figure 2 summarizes
the basic function of the part.
(continued on page 2)
ANALOG
VIDEO
SIGNAL
OR
IMAGE
SENSOR
SIGNAL
ADV7185
DECODER
DIGITIZER
ADV611/
ADV612
ADSP-21xx
SERIAL
OR PARALLEL
BITSTREAM FOR
TRANSMISSION
OR STORAGE
QUALITY BOX CONTROLS
FROM REMOTE SITE
Figure 1. Typical Application
8
COMPONENT
VIDEO I/O
FUNCTIONAL BLOCK DIAGRAM
ADV611/
ADV612
LOCATION, SIZE AND CONTRAST CONTROL
ON-CHIP
TRANSFORM
BUFFER
SUBBAND STATISTICS
DIGITAL
VIDEO
I/O PORT
QUALITY
BOX
CONTROL
WAVELET
FILTERS,
DECIMATOR &
INTERPOLATOR
QUANTIZER
& ENTROPY
CODING
HOST
I/O PORT
& FIFO
DRAM
MANAGER
BIN WIDTH CONTROL
16/32
HOST
256K ؋ 16-BIT DRAM
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999







ADV611 pdf, 数据表
ADV611/ADV612
THE PROGRAMMABLE QUANTIZER
This block quantizes the filtered image based on the response
profile of the human visual system. In general, the human eye
cannot resolve high frequencies in images to the same level of
accuracy as lower frequencies. Through intelligent “quantiza-
tion” of information contained within the filtered image, the
ADV611/ADV612 achieves compression without compromising
the visual quality of the image. Figure 9 shows the encode and
decode data formats used by the quantizer.
Figure 10 shows how a typical quantization pattern applies over
Mallat block data. The high frequency blocks receive much
larger quantization (appear darker) than the low frequency
blocks (appear lighter). Looking at this figure, one sees some key
point concerning quantization: (1) quantization relates directly
to frequency in Mallat block data and (2) levels of quantization
range widely from high to low frequency block. (Note that the
fill is based on a log formula.) The relation between actual
ADV611/ADV612 bin width factors and the Mallat block fill
pattern in Figure 10 appears in Table III.
9.7
WAVELET
DATA
QUANTIZER - ENCODE MODE
15.17 DATA
SIGNED SIGNED
UNSIGNED
6.10
1/BW
0.5
1/BW
TRNC
15.0 BIN
NUMBER
15.0 BIN
NUMBER
QUANTIZER - DECODE MODE
SIGNED SIGNED
23.8
DE-QUANTIZED
WAVELET DATA
SAT
UNSIGNED
8.8 BW
BW
9.7
WAVELET
DATA
Figure 9. Programmable Quantizer Data Flow
39 33
36 30
27
24
21
18
15
12
Y COMPONENT
6
0
93
40 34
37 31
25
28 22
16
19 13
10
Cb COMPONENT
7
1
4
41 35
38 32
26
29 23
17
20 14
11
Cr COMPONENT
8
2
5 QUANTIZATION OF MALLAT BLOCKS
LOW
HIGH
Figure 10. Typical Quantization of Mallat Data Blocks (Graphed)
–8–
REV. 0







ADV611 equivalent, schematic
ADV611/ADV612
Sum of Luma Value Register
Indirect (Read Only) Register Index 0x0AA
The Sum of Luma Value register lets the host or DSP read the sum of pixel values for the Luma component in block 39. The
Host reads these values through the Host Interface.
[15:0] Sum of Luma, SL[15:0]. 16-bit component pixel values (undefined at reset)
[31:0] Reserved (always read zero)
Sum of Cb Value Register
Indirect (Read Only) Register Index 0x0AB
The Sum of Cb Value register lets the host or DSP read the sum of pixel values for the Cb component in block 40. The Host
reads these values through the Host Interface.
[15:0] Sum of Cb, SCB[15:0]. 16-bit component pixel values (undefined at reset)
[31:0] Reserved (always read zero)
Sum of Cr Value Register
Indirect (Read Only) Register Index 0x0AC
The Sum of Cr Value register lets the host or DSP read the sum of pixel values for the Cr component in block 41. The Host
reads these values through the Host Interface.
[15:0] Sum of Cr, SCR[15:0]. 16-bit component pixel values (undefined at reset)
[31:0] Reserved (always read zero)
MIN Luma Value Register
Indirect (Read Only) Register Index 0x0AD
The MIN Luma Value register lets the host or DSP read the minimum pixel value for the Luma component in the unprocessed
data. The Host reads these values through the Host Interface.
[15:0] Minimum Luma, MNL[15:0]. 16-bit component pixel value (undefined at reset)
[31:0] Reserved (always read zero)
MAX Luma Value Register
Indirect (Read Only) Register Index 0x0AE
The MAX Luma Value register lets the host or DSP read the maximum pixel value for the Luma component in the unprocessed
data. The Host reads these values through the Host Interface.
[15:0] Maximum Luma, MXL[15:0]. 16-bit component pixel value (undefined at reset)
[31:0] Reserved (always read zero)
MIN Cb Value Register
Indirect (Read Only) Register Index 0x0AF
The MIN Cb Value register lets the host or DSP read the minimum pixel value for the Cb component in the unprocessed data.
The Host reads these values through the Host Interface.
[15:0] Minimum Cb, MNCB[15:0], 16-bit component pixel value (undefined at reset)
[31:0] Reserved (always read zero)
MAX Cb Value Register
Indirect (Read Only) Register Index 0x0B0
The MAX Cb Value register lets the host or DSP read the maximum pixel value for the Cb component in the unprocessed data.
The Host reads these values through the Host Interface.
[15:0] Maximum Cb, MXCB[15:0].16-bit component pixel value (undefined at reset)
[31:0] Reserved (always read zero)
–16–
REV. 0










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