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零件编号 | AL128 | ||
描述 | Plug and Play VGA to NTSC/PAL Converter | ||
制造商 | ETC | ||
LOGO | |||
1 Page
AL128 Data Sheets
AL128
MWENL
out (CMOS)
78
Memory Low Byte Write Enable
MWRST
out (CMOS)
71
Memory Write Reset
PAL
in (CMOSd)
2
NTSC/PAL select
0 - NTSC
1 - PAL
RED<7:0>
in (CMOSd)
100-107
Graphic Red input data
RGBOUT
in (CMOSd)
1
RGB/YC Composite output select
0 - ACMP, AY, AC
1 - R, G, B
RSET
SCL
SDA
in 42
in (CMOSsu)
13
in/out (CMOSsu) 10
DAC Full scale current adjust, 82 ohm pull-
down for S-video and Composite output, 140
ohm pull-down for RGB output.
I2C Clock
I2C Data
SELECT
in (CMOSsd)
5
Select button
TEST1~12
out (CMOS)
9, 15-18, 20- Unused pins for factory test purpose only
23, 25,26,33
TVCSYNC
out (CMOS)
32
TV composite sync
TVHSYNC
out (CMOS)
30
TV horizontal sync
TVVSYNC
out (CMOS)
31
TV vertical sync
TVCLK
out (CMOS)
151
Clock output for graphic chip clock
VRB
in (0 V)
135
ADC Bottom Voltage Reference
VREF
in (1.23 V)
35
DAC Voltage Reference Input
VRT
in
134 ADC Top Voltage Reference
XIN1/FIN1
in (CMOS)
159
Crystal Input/External Clock Input 1 for
NTSC
XIN2/FIN2
in (CMOS)
154
Crystal Input/External Clock Input 2 for PAL
XOUT1
out (CMOS)
158
Crystal Output 1 for NTSC
XOUT2
out (CMOS)
153
Crystal Output 2 for PAL
Power and Ground
VDD x 13
5V
8, 24, 46, 61,
70, 79, 89, 99,
113, 123, 139,
144, 150
Digital power
April 2, 1999
8
VGA Input
HSYNC
H total (Reg # 28h)
H Pan Delta (Reg # 21h), (Reg # 2Bh for Zoom)
H Capture Size (Reg # 23h)
Default Capture Start
H-display Delta (Reg # 52h)
TV Output
* Scaled up ratio defined in Reg # 27h
Default Horizontal
Display Start
TVHSYNC
Horizontal Display Size (Horizontal
Active Region Shown on TV)
Al128-16 Timing_horizontal
AL128
Vertical capture and display timing is as follows:
April 2, 1999
16
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页数 | 45 页 | ||
下载 | [ AL128.PDF 数据手册 ] |
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