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PDF ( 数据手册 , 数据表 ) AK2306LV

零件编号 AK2306LV
描述 Dual PCM CODEC for ISDN/VoIP TERMINAL ADAPTER
制造商 Asahi Kasei Microsystems
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AK2306LV 数据手册, 描述, 功能
ASAHI KASEI
[AK2306/LV]
AK2306/2306LV
Dual PCM CODEC for ISDN/VoIP TERMINAL ADAPTER
GENERAL DESCRIPTION
AK2306 is a dual PCM CODEC-Filter most suitable for
ISDN Terminal Adapter.
It includes Selectable A-law/u-law function, Internal
Gain Adjustment from +6dB to –18dB by 1dB step
control, Selectable 16Hz/20Hz Ring Tone Generator for
SLIC. All of these functions are controlled by the
internal register accessed through the serial interface.
PCM interface of AK2306 accepts Long Frame, Short
Frame clock formats and GCI format. 64 x N
kHz(128k-4096kHz) clock input is available for PCM
interface.
AK2306 and AK2306LV are pin-compatible, but
different products which power supply voltage are 5.0V
and 3.3V,respectively.
FEATURE
- Dual PCM CODEC and Filtering systems for
ISDN Terminal Adapter
- Selectable Ring Tone Generator for SLIC
16Hz or 20Hz tone is available.
- Independent functions on each channel
controlled by the internal register
- Power Down Mode
- Mute
- Gain Adjustment: +6 to -18dB (1dB step)
- Selectable PCM Data Interface Timing:
Long Frame / Short Frame/GCI
- Variable PCM Data Rate:
64k x N [Hz] (128k - 4.096MHz)
- OP Amp for External Gain Adjustment
- A-law/u-law Register Selectable
- Serial Interface to access the internal register
- Power on Reset
- Single Power Supply Voltage
- +5.0V ± 5% (AK2306)
- +3.3V ± 0.3V (AK2306LV)
- Low Power Consumption
PACKAGE
- 24pinVSOP
7.9 x 7.6 mm (0.5mm pin pitch)
MS0093-E-04 1 2001/11







AK2306LV pdf, 数据表
ASAHI KASEI
[AK2306/LV]
CIRCUIT DESCRIPTION
Block
AMPT0,1
AMPR0,1
AAF
A/D
D/A
SMF
BGREF
RING TONE
GENERATOR
GA0T/R
GA1T/R
GATN
SERIAL I/F
PLL
PCM I/F
Function
Op-amp for input gain adjustment. This op-amp has differential inputs.
Adjusting the gain with external resistors. The resistor larger than 10kis
recommended for the feedback resistor.
<NOTE>
AMPT0(1) becomes automatically power down, when CODEC ch0(1) is power
down.
Op-amp for output gain adjustment. This op-amp is used as an inverting
amplifier. Adjusting the gain with external resistors. The resistor larger than
10kis recommended for the feedback resistor.
Integrated anti-aliasing filter which prevents signals around the sampling rate
from folding back into the voice band. AAF is a 2nd order RC low-pass filter.
Converts analog signal to 8bit PCM data according to the companding schemes of
ITU recommendation G.711; A-law or u-law. The band limiting filter is also
integrated. The selection of companding schemes is set by ALAWN register as
follows:
"H": u-Law
"L": A-Law
Expands 8bit PCM data according to A-law or u-law. The selection of
companding schemes is set by ALAWN register as follows:
"H": u-Law
"L": A-Law
Extracts the inband signal from D/A output. It also corrects the sinx/x effect of
D/A output.
Provides the stable analog ground voltage using an on-chip band-gap reference
circuit which is temperature compensated. The output voltage is 2.4V for +5V
operation(AK2306) or 1.5V for +3.3V operation(AK2306LV).
Generates two kinds of tone; 16Hz or 20Hz. Tone selection and Tone ON/OFF is
controlled by the registers.
Gain selects of analog I/O signals. It is posibble to select gain from +6dB to -18dB
(1dB/step). Gain is defined by the internal register.
Interface to the internal register by using SCLK, DATA, and CSN pins.
PLL generates system clock of AK2306. Reference clock is FS (8KHz). More than
0.22uF of an external capacitance should be connected between LPC and VSS.
PCM data rate is available for 64xN(N = 2 to 64)kHz which synchronizes with
BCLK. Two kinds of data format (Long Frame, Short Frame) are available.
Each data format is automatically detected. PCM data stream, which includes
ch0 and ch1 data, is output through DX pin and input through DR pin. Ch1
PCM data stream always follows ch0 PCM data stream.
MS0093-E-04 8 2001/11







AK2306LV equivalent, schematic
ASAHI KASEI
[AK2306/LV]
POWER DOWN
Power consumption is reduced in the power down mode.
In the power down mode, the current fed to analog circuits and the clock for digital circuits, are stopped, and the
relating circuits hold its status.
There are two power down modes.
- Power down for all circuits
- Power down by block
* In the power down mode, the output pins of corresponding blocks turn to Hi-Z except TNOUT pin.(See page 5)
POWER DOWN MODE SETTING
2 power down modes
Mode
Circuits Registers Operation for “0”/”1”
Note
All circuit
All
PD
”0” : Normal
”1” : Power down
- CPU Registers are not reset.
- Serial I/F is available.
- No need to supply FS, BCLK.
CODEC
CH0
PDCH0
Block
CODEC
CH1
PDCH1
”0” : Normal
”1” : Power down
RING
TONEGEN
PDTN
- Keep supplying FS, even when CODEC
CH0,1 are in power down mode (see
page10,11).
- When CODEC CHn(n=0,1) is in power
down mode, the functions below are active:
(1) AMPTn(n=0,1) Input/Output
(2) TNOUT Output
Please refer next page table in deltail.
CANCELLATION OF POWER DOWN : CODEC
When power down mode for CODEC CH0/CH1 is cleared, the CODEC circuitry starts to be initialized.
It takes 130mS(typ.).
When full circuit power down mode for CODEC is cleared, AK2306/LV starts the same wake up sequence as
one at power on. It takes 250ms(Typ)
Wake up time for Tone generator is 125us(Typ).
MS0093-E-04 16 2001/11










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