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PDF ( 数据手册 , 数据表 ) ADV7301A

零件编号 ADV7301A
描述 Multiformat SD/ Progressive Scan/HDTV Video Encoder
制造商 Analog Devices
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ADV7301A 数据手册, 描述, 功能
a
Multiformat SD, Progressive Scan/HDTV
Video Encoder with Six NSV12-Bit DACs
ADV7300A/ADV7301A
FEATURES
High Definition Input Formats
YCrCb Compliant to SMPTE293M (525 p),
ITU-R.BT1358 (625 p), SMPTE274M (1080 i),
SMPTE296M (720 p), and Any Other High Definition
Standard Using Async Timing Mode
RGB in 3 ؋ 10-Bit 4:4:4 Format
BTA T-1004 EDTV2 525 p Parallel
High Definition Output Formats (525 p/625 p/720 p/1080 i)
YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA 770.3)
RGB + H/V (HDTV 5-Wire Format)
CGMS-A (720 p/1080 i)
Macrovision Rev 1.0 (525 p/625 p)*
CGMS-A (525 p)
Standard Definition Input Formats
CCIR-656 4:2:2 8-/10-Bit Parallel Input
CCIR-601 4:2:2 16-/20-Bit Parallel Input
Standard Definition Output Formats
Composite NTSC M, N;
PAL M, N, B, D, G, H, I, PAL-60
SMPTE170M NTSC Compatible Composite Video
ITU-R.BT470 PAL Compatible Composite Video
S-Video (Y/C)
EuroScart RGB
Component YUV (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1*
CGMS/WSS
Closed Captioning
GENERAL FEATURES
Simultaneous SD and HD Inputs and Outputs
Oversampling (108 MHz/148.5 MHz)
On-Board Voltage Reference
6 NSV Precision Video 12-Bit DACs
2-Wire Serial MPU Interface
Dual I/O Supply 2.5 V/3.3 V Operation
Analog and Digital Supply 2.5 V
On-Board PLL
64-LQFP Package
Lead-Free Product
APPLICATIONS
High End DVD Players
SD/Program Scan/HDTV Display Devices
SD/Program Scan/HDTV Set-Top Boxes
SD/HDTV Studio Equipment
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
S9–S0
Y9–Y0
C9–C0
S_HSYNC
S_VSYNC
S_BLANK
P_HSYNC
P_VSYNC
P_BLANK
CLKIN_A
CLKIN_B
STANDARD DEFINITION
CONTROL BLOCK
COLOR CONTROL
D BRIGHTNESS
E DNR
M GAMMA
U PROGRAMMABLE FILTERS
X SD TEST PATTERN
PROGRAMMABLE
RGB MATRIX
D
E
M
U
X
TIMING
GENERATOR
HIGH DEFINITION
CONTROL BLOCK
HD TEST PATTERN
COLOR CONTROL
ADAPTIVE FILTER CTRL
SHARPNESS FILTER
PLL
ADV7300A/
ADV7301A
12-BIT
DAC
O 12-BIT
V DAC
E
R
S
A
12-BIT
DAC
M
P 12-BIT
L DAC
I
N 12-BIT
G DAC
12-BIT
DAC
I2C
INTERFACE
GENERAL DESCRIPTION
The ADV7300A/ADV7301A is a high speed, digital-to-analog
encoder on a single monolithic chip. It includes six high speed
video D/A converters with TTL compatible inputs.
The ADV7300A/ADV7301A has three separate 10-bit wide input
ports that accept data in high definition and/or standard defini-
tion video format. For all standards, external horizontal, vertical,
and blanking signals, or EAV/SAV timing codes, control the
insertion of appropriate synchronization signals into the digital
data stream and therefore the output signals.
NSV (Noise Shaped Video) is a trademark of Analog Devices, Inc.
*ADV7300A Only
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002







ADV7301A pdf, 数据表
ADV7300A/ADV7301A
CLKIN_A
CONTROL
I/PS
P_HSYNC,
P_VSYNC,
P_BLANK
Y9–Y0
CONTROL
O/PS
S_HSYNC,
S_VSYNC
t9 t10
Cb0
t12
t11
Y0
Cr0 Y1
t13
t14
Crxxx
Yxxx
t9 = CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME
Figure 6. PS 4:2:2 1 ϫ 10-Bit Interleaved @ 54 MHz, Input Mode: PS 54 MHz Input (Input
Mode at Subaddress 01h = 111)
CLKIN_A
CONTROL
I/PS
S_HSYNC,
S_VSYNC,
S_BLANK
t9 t10
t12
IN SLAVE
MODE
S9–S2
Cb Y Cr Y Cb Y
CONTROL
O/PS
S_HSYNC,
S_VSYNC
t11 t13
t14
IN MASTER/SLAVE
MODE WITH
EAV/SAV
Figure 7. 8-Bit SD Pixel Input Timing Diagram, Input Mode: SD Input Only (Input Mode at Subaddress 01h = 000)
–8– REV. A







ADV7301A equivalent, schematic
ADV7300A/ADV7301A
Table I. Power Mode Register
Subaddress Register
Bit Description
00h Power Mode Register Sleep Mode1
PLL and Oversampling
Control2
DAC F: Power On/Off
DAC E: Power On/Off
DAC D: Power On/Off
DAC C: Power On/Off
DAC B: Power On/Off
DAC A: Power On/Off
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0 Sleep Mode Off
1 Sleep Mode On
0 PLL On
1
0
1
0
1
0
1
0
1
0
1
0
1
PLL Off
DAC F Off
DAC F On
DAC E Off
DAC E On
DAC D Off
DAC D On
DAC C Off
DAC C On
DAC B Off
DAC B On
DAC A Off
DAC A On
Reset
Fch
NOTES
1When enabled, the current consumption is reduced to µA level. All DACs and the internal PLL circuit are disabled. I2C registers can be read from and written to.
2This control allows the internal PLL circuit to be powered down and the oversampling to be switched off.
Table II. Input Mode Register
Subaddress Register
Bit Description
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
Reset
01h Input Mode Register BTA T-1004 Compatibility
0 Disabled
38h
1 Enabled
Reserved
Pixel Align
Clock Align
0
0
1
0
Zero must be written
to this bit.
Video input data starts
with a Y0 bit. Only for
PS Interleaved Mode.
Video input data starts
with a Cb0 bit.
Input Mode
1
000
Must be set if the
phase delay between
the two input clocks is
<9.25 ns or >27.75 ns.
Only if two input
clocks are used.
SD Input Only
001
PS Input Only
010
HDTV Input Only
011
SD and PS (20-Bit)
100
SD and PS (10-Bit)
101
110
SD and HDTV (SD
Oversampled)
SD and HDTV
(HDTV Oversampled)
Reserved
111
0
PS 54 MHz Input
Zero must be written
to this bit.
–16–
REV. A










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