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PDF ( 数据手册 , 数据表 ) ADV7197

零件编号 ADV7197
描述 Multiformat HDTV Encoder with Three 11-Bit DACs
制造商 Analog Devices
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ADV7197 数据手册, 描述, 功能
a
Multiformat HDTV Encoder with
Three 11-Bit DACs
ADV7197
FEATURES
INPUT FORMATS
YCrCb in 2 ؋ 10-Bit (4:2:2) or 3 ؋ 10-Bit (4:4:4) Format
Compliant to SMPTE274M (1080i), SMPTE296M
(720p) and Any Other High-Definition Standard Using
Async Timing Mode
RGB in 3 ؋ 10-Bit 4:4:4 Format
OUTPUT FORMATS
YPrPb HDTV (EIA-770.3)
RGB Levels Compliant to RS-170 and RS-343A
11-Bit + Sync (DAC A)
11-Bit DACs (DAC B, C)
PROGRAMMABLE FEATURES
Internal Test Pattern Generator with Color Control
Y/C Delay (؎)
Individual DAC On/Off Control
VBI Open Control
I2C Filter
2-Wire Serial MPU Interface
Single Supply 5 V/3.3 V Operation
52-Lead MQFP Package
APPLICATIONS
HDTV Display Devices
HDTV Projection Systems
Digital Video Systems
High Resolution Color Graphics
Image Processing/Instrumentation
Digital Radio Modulation/Video Signal Reconstruction
Y0–Y9
Cr0–Cr9
Cb0–Cb9
CLKIN
HORIZONTAL
SYNC
VERTICAL
SYNC
BLANKING
RESET
FUNCTIONAL BLOCK DIAGRAM
TEST
PATTERN
GENERATOR
AND
DELAY
CHROMA
4:2:2 TO 4:4:4
(SSAF)
CHROMA
4:2:2 TO 4:4:4
(SSAF)
11-BIT
+ SYNC
DAC
11-BIT
DAC
11-BIT
DAC
SYNC
GENERATOR
TIMING
GENERATOR
DAC CONTROL
BLOCK
I2C MPU
PORT
ADV7197
DAC A (Y)
DAC B
DAC C
VREF
RSET
COMP
GENERAL DESCRIPTION
The ADV7197 is a triple, high-speed, digital-to-analog encoder
on a single monolithic chip. It consists of three high-speed video
D/A converters with TTL-compatible inputs.
The ADV7197 has three separate 10-bit-wide input ports that
accept data in 4:4:4 10-bit YCrCb or RGB, or 4:2:2 10-bit
YCrCb. This data is accepted in HDTV format at 74.25 MHz
or 74.1758 MHz. For any other high definition standard but
SMPTE274M or SMPTE296M, the Async Timing Mode can
be used to input data to the ADV7197. For all standards,
external horizontal, vertical, and blanking signals or EAV/SAV
codes control the insertion of appropriate synchronization signals
into the digital data stream and therefore the output signals.
The ADV7197 outputs analog YPrPb HDTV complying to
EIA-770.3, or RGB complying to RS-170/RS-343A.
The ADV7197 requires a single 5 V/3.3 V power supply, an
optional external 1.235 V reference, and a 74.25 MHz (or
74.1758 MHz) clock.
The ADV7197 is packaged in a 52-lead MQFP package.
*ADV is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001







ADV7197 pdf, 数据表
ADV7197
ABSOLUTE MAXIMUM RATINGS1
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Pin . . . . GND – 0.5 V to VAA + 0.5 V
Ambient Operating Temperature (TA) . . . . . –40°C to +85°C
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . 150°C
Infrared Reflow Soldering (20 secs) . . . . . . . . . . . . . . . 225°C
Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . 220°C
IOUT to GND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VAA
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
Model
ADV7197KST
Temperature Range
0°C to 70°C
ORDERING GUIDE
Package Description
Plastic Quad Flatpack (MQFP)
Package Option
S-52
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADV7197 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
52 51 50 49 48 47 46 45 44 43 42 41 40
VDD 1
Y[0] 2
Y[1] 3
Y[2] 4
Y[3] 5
Y[4] 6
Y[5] 7
Y[6] 8
Y[7] 9
Y[8] 10
Y[9] 11
VDD 12
GND 13
PIN 1
IDENTIFIER
ADV7197
TOP VIEW
(Not to Scale)
39 VREF
38 RSET
37 COMP
36 DAC B
35 VAA
34 DAC A
33 AGND
32 DAC C
31 SDA
30 SCL
29 HSYNC/SYNC
28 VSYNC/TSYNC
27 DV
14 15 16 17 18 19 20 21 22 23 24 25 26
–8– REV. 0







ADV7197 equivalent, schematic
ADV7197
COLOR Y
CY (CY7–CY0)
(Address (SR4–SR0) = 06H)
CY7 CY6 CY5 CY4 CY3 CY2 CY1 CY0
CY7–CY0
COLOR Y VALUE
Figure 21. Color Y Register
COLOR CR
CCR (CCR7–CCR0)
(Address (SR4–SR0) = 07H)
CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0
CCR7CCR0
COLOR CR VALUE
Figure 22. Color Cr Register
COLOR CB
CCB (CCB7–CCB0)
(Address (SR4–SR0) = 08H)
CCB7 CCB6 CCB5 CCB4 CCB3 CCB2 CCB1 CCB0
CCB7CCB0
COLOR CB VALUE
Figure 23. Color Cb Register
These three 8-bit-wide registers are used to program the output
color of the internal test pattern generator, be it the lines of the
cross hatch pattern or the uniform field test pattern.
The standard used for the values for Y and the color difference
signals to obtain white, black and the saturated primary and comple-
mentary colors conforms to the ITU-R BT 601-4 standard.
The Table III shows sample color values to be programmed into
the color registers.
Sample
Color
White
Black
Red
Green
Blue
Yellow
Cyan
Magenta
Table III. Sample Color Values
Color Y
Value
235 (EB)
16 (10)
81 (51)
145 (91)
41 (29)
210 (D2)
170 (AA)
106 (6A)
Color Cr
Value
128 (80)
128 (80)
240 (F0)
34 (22)
110 (6E)
146 (92)
16 (10)
222 (DE)
Color Cb
Value
128 (80)
128 (80)
90 (5A)
54 (36)
240 (F0)
16 (10)
166 (A6)
202 (CA)
DAC TERMINATION AND LAYOUT CONSIDERATIONS
Voltage Reference
The ADV7197 contains an on-board voltage reference. The
VREF pin is normally terminated to VAA through a 0.1 µF capacitor
when the internal VREF is used. Alternatively, the ADV7197
can be used with an external VREF (AD589).
Resistor RSET is connected between the RSET pin and analog
ground and is used to control the full scale output current and
therefore the DAC voltage output levels. For full-scale output
RSET must have a value of 2470 . RLOAD has a value of 300 .
When an input range of 0–1023 is selected the value of RSET
must be 2820 .
The ADV7197 has three analog outputs, corresponding to Y,
Pr, Pb video signals. The DACs must be used with external
buffer circuits in order to provide sufficient current to drive an
output device. A suitable op amp would be the AD8057.
PC BOARD LAYOUT CONSIDERATIONS
The ADV7197 is optimally designed for lowest noise perfor-
mance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7197, it is imperative
that great care be given to the PC board layout.
The layout should be optimized for lowest noise on the ADV7197
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of VAA and AGND and VDD and DGND pins
should be kept as short as possible to minimized inductive ringing.
It is recommended that a four-layer printed circuit board is
used. With power and ground planes separating the layer of the
signal carrying traces of the components and solder side layer.
Placement of components should consider to separate noisy
circuits, such as crystal clocks, high-speed logic circuitry and
analog circuitry.
There should be a separate analog ground plane (AGND) and
a separate digital ground plane (GND).
Power planes should encompass a digital power plane (VDD) and a
analog power plane (VAA). The analog power plane should contain
the DACs and all associated circuitry, and the VREF circuitry.
The digital power plane should contain all logic circuitry. The
analog and digital power planes should be individually connected
to the common power plane at one single point through a suit-
able filtering device, such as a ferrite bead.
DAC output traces on a PCB should be treated as transmission
lines. It is recommended that the DACs be placed as close as
possible to the output connector, with the analog output traces
being as short as possible (less than 3 inches. The DAC termi-
nation resistors should be placed as close as possible to the DAC
outputs and should overlay the PCB’s ground plane. As well as
minimizing reflections, short analog output traces will reduce
noise pickup due to neighboring digital circuitry.
–16–
REV. 0










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