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PDF ( 数据手册 , 数据表 ) ADV7181

零件编号 ADV7181
描述 Multiformat SDTV Video Decoder
制造商 Analog Devices
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ADV7181 数据手册, 描述, 功能
FEATURES
Multiformat video decoder supports NTSC-(J, M, 4.43),
PAL-(B/D/G/H/I/M/N), SECAM
Integrates three 54 MHz, 9-bit ADCs
Clocked from a single 27 MHz crystal
Line-locked clock-compatible (LLC)
Adaptive Digital Line Length Tracking (ADLLT™)
5-line adaptive comb filters
Proprietary architecture for locking to weak, noisy, and
unstable video sources such as VCRs and tuners
Subcarrier frequency lock and status information output
Integrated AGC with adaptive peak white mode
Macrovision® copy protection detection
CTI (chroma transient improvement)
DNR (digital noise reduction)
Multiple programmable analog input formats:
CVBS (composite video)
S-Video (Y/C)
YPrPb component (VESA, MII, SMPTE, and Betacam)
6 analog video input channels
Automatic NTSC/PAL/SECAM identification
Digital output formats (8-bit or16-bit):
ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD
0.5 V to 1.6 V analog signal input range
Differential gain: 0.6% typ
GENERAL DESCRIPTION
The ADV7181 integrated video decoder automatically detects
and converts a standard analog baseband television signal
compatible with worldwide standards NTSC, PAL, and SECAM
into 4:2:2 component video data compatible with 16-/8-bit
CCIR601/CCIR656.
The advanced, highly flexible digital output interface enables
performance video decoding and conversion in line-locked
clock-based systems. This makes the device ideally suited for a
broad range of applications with diverse analog video charac-
teristics, including tape-based sources, broadcast sources,
security/surveillance cameras, and professional systems.
The six analog input channels accept standard composite,
S-Video, YPrPb video signals in an extensive number of
combinations. AGC and clamp restore circuitry allow an input
video signal peak-to-peak range of 0.5 V up to 1.6 V.
Alternatively, these can be bypassed for manual settings.
Multiformat SDTV Video Decoder
ADV7181
Differential phase: 0.6° typ
Programmable video controls:
Peak-white/hue/brightness/saturation/contrast
Integrated on-chip video timing generator
Free run mode (generates stable video ouput with no I/P)
VBI decode support for
Close captioning, WSS, CGMS, EDTV, Gemstar® 1×/2×
Power-down mode
2-wire serial MPU interface (I2C®-compatible)
3.3 V analog, 1.8 V digital core; 3.3 V IO supply
Temperature grade: –40°C to +85°C
64-lead LQFP Pb-free package
APPLICATIONS
DVD recorders
PC video
HDD-based PVRs/DVDRs
LCD TVs
Set-top boxes
Security systems
Digital televisions
Portable video devices
Automotive entertainment
AVR receiver
The fixed 54 MHz clocking of the ADCs and datapath for all
modes allow very precise, accurate sampling and digital
filtering. The line-locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line locked even with ±5% line length
variation. The output control signals allow glueless interface
connections in almost any application. The ADV7181 modes
are set up over a 2-wire, serial, bidirectional port (I2C-
compatible).
The ADV7181 is fabricated in a 3.3 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation.
The ADV7181 is packaged in a small 64-lead LFCSP and LQFP
and Pb-free packages.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.







ADV7181 pdf, 数据表
ADV7181
TIMING SPECIFICATIONS
Guaranteed by characterization. AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V; operating
temperature range, unless otherwise noted.
Table 3.
Parameter
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
Frequency Stability
I2C PORT
SCLK Frequency
SCLK Min Pulse Width High
SCLK Min Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time for Stop Condition
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC1 Mark Space Ratio
DATA AND CONTROL OUTPUTS
Data Output Transitional Time
Data Output Transitional Time
Symbol Test Conditions
t1
t2
t3
t4
t5
t6
t7
t8
t9:t10
t11
t12
Negative clock edge to start of valid data.
(tACCESS = t10 – t11)
End of valid data to negative clock edge.
(tHOLD = t9 + t12)
Min Typ Max Unit
27.00
±50
MHz
ppm
0.6
1.3
0.6
0.6
100
0.6
400 kHz
µs
µs
µs
µs
ns
300 ns
300 ns
µs
5 ms
45:55
55:45 % Duty Cycle
6 ns
0.6 ns
ANALOG SPECIFICATIONS
Guaranteed by characterization. At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V;
operating temperature range, unless otherwise noted. Recommended analog input video signal range: 0.5 V – 1.6 V, typically 1 V p-p.
Table 4.
Parameter
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
Symbol Test Conditions
Clamps switched off
Min Typ Max Unit
0.1 µF
10 MΩ
0.75 mA
0.75 mA
60 µA
60 µA
THERMAL SPECIFICATIONS
Table 5.
Parameter
THERMAL CHARACTERISTICS
Junction-to-Ambient Thermal
Resistance (Still Air)
Junction-to-Case Thermal Resistance
Junction-to-Ambient Thermal
Resistance (Still Air)
Junction-to-Case Thermal Resistance
Symbol Test Conditions
θJA 4-layer PCB with solid ground plane, 64-lead LFCSP
θJC 4-layer PCB with solid ground plane, 64-lead LFCSP
θJA 4-layer PCB with solid ground plane, 64-lead LQFP
θJC 4-layer PCB with solid ground plane, 64-lead LQFP
Rev. B | Page 8 of 104
Min Typ Max Unit
45.5 °C/W
9.2 °C/W
47 °C/W
11.1 °C/W







ADV7181 equivalent, schematic
ADV7181
GLOBAL PIN CONTROL
Three-State Output Drivers
TOD, Address 0x03 [6]
This bit allows the user to three-state the output drivers of the
ADV7181.
Upon setting the TOD bit, the P15–P0, HS, VS, FIELD, and SFL
pins are three-stated.
The timing pins (HS/VS/FIELD) can be forced active via the
TIM_OE bit. For more information on three-state control, refer
to the following sections:
Three-State LLC Driver
Timing Signals Output Enable
Individual drive strength controls are provided via the
DR_STR_XX bits.
Table 16. TOD Function
TOD Description
0 (default)
Output drivers enabled.
1 Output drivers three-stated.
Three-State LLC Driver
TRI_LLC, Address 0x0E [6]
This bit allows the output drivers for the LLC pin of the
ADV7181 to be three-stated. For more information on three-
state control, refer to the following sections:
Three-State Output Drivers
Timing Signals Output Enable
Individual drive strength controls are provided via the
DR_STR_XX bits.
Table 17. TRI_LLC Function
TRI_LLC
Description
0 (default)
LLC pin drivers working according to the
DR_STR_C[1:0] setting (pin enabled).
1 LLC pin drivers three-stated.
Timing Signals Output Enable
TIM_OE, Address 0x04 [3]
The TIM_OE bit should be regarded as an addition to the TOD
bit. Setting it high forces the output drivers for HS, VS, and
FIELD into the active (that is, driving) state even if the TOD bit
is set. If set to low, the HS, VS, and FIELD pins are three-stated
depending on the TOD bit. This functionality is useful if the
decoder is to be used as a timing generator only. This may be
the case if only the timing signals are to be extracted from an
incoming signal, or if the part is in free-run mode where a
separate chip can output, for instance, a company logo.
For more information on three-state control, refer to the
following sections:
Three-State Output Drivers
Three-State LLC Driver
Individual drive strength controls are provided via the
DR_STR_XX bits.
Table 18. TIM_OE Function
TIM_OE
Description
0 (default)
HS, VS, FIELD three-stated according to the
TOD bit.
1 HS, VS, FIELD are forced active all the time. The
DR_STR_S[1:0] setting determines drive
strength.
Drive Strength Selection (Data)
DR_STR[1:0] Address 0x04 [5:4]
For EMC and crosstalk reasons, it may be desirable to
strengthen or weaken the drive strength of the output drivers.
The DR_STR[1:0] bits affect the P[15:0] output drivers.
For more information on three-state control, refer to the
following sections:
Drive Strength Selection (Clock)
Drive Strength Selection (Sync)
Table 19. DR_STR Function
DR_STR[1:0] Description
00 Low drive strength (1×).
01 (default)
Medium low drive strength (2×).
10 Medium high drive strength (3×).
11 High drive strength (4×).
Rev. B | Page 16 of 104










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