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PDF ( 数据手册 , 数据表 ) ADV7178

零件编号 ADV7178
描述 Integrated Digital CCIR-601 to PAL/NTSC Video Encoder
制造商 Analog Devices
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ADV7178 数据手册, 描述, 功能
Integrated Digital CCIR-601
to PAL/NTSC Video Encoder
ADV7177/ADV7178
FEATURES
ITU-R BT601/656 YCrCb to PAL/NTSC video encoder
High quality, 9-bit video DACs
Integral nonlinearity <1 LSB at 9 bits
NTSC-M, PAL-M/N, PAL-B/D/G/H/I
Single 27 MHz crystal/clock required (±2 oversampling)
75 dB video SNR
32-bit direct digital synthesizer for color subcarrier
Multistandard video output support:
Composite (CVBS)
Component S-video (Y/C)
Component YUV or RGB
Video input data port supports:
CCIR-656 4:2:2 8-bit parallel input format
4:2:2 16-bit parallel input format
Full video output drive or low signal drive capability
34.7 mA max into 37.5 Ω (doubly terminated 75 R)
5 mA min with external buffers
Programmable simultaneous composite and S-VHS
(VHS) Y/C or RGB (SCART)/YUV video outputs
Programmable luma filters (low-pass/notch/extended)
Programmable VBI (vertical blanking interval)
Programmable subcarrier frequency and phase
Programmable luma delay
Individual on/off control of each DAC
CCIR and square pixel operation
Color-signal control/burst-signal control
Interlaced/noninterlaced operation
Complete on-chip video timing generator
OSD support (ADV7177 only)
Programmable multimode master/slave operation
Macrovision AntiTaping Rev. 7.01 (ADV7178 only)1
Closed captioning support
On-board voltage reference
2-wire serial MPU interface (I2C®-compatible)
Single-supply 5 V or 3 V operation
Small 44-lead MQFP package
Synchronous 27 MHz/13.5 MHz clock output
APPLICATIONS
MPEG-1 and MPEG-2 video, DVD, digital satellite,
cable systems (set-top boxes/IRDs), digital TVs,
CD video/karaoke, video games, PC video/multimedia
1 The Macrovision anticopy process is licensed for noncommercial home use
only, which is its sole intended use in the device. Please contact sales office
for latest Macrovision version available. ITU-R and CCIR are used inter-
changeably in this document (ITU-R has replaced CCIR recommendations).
FUNCTIONAL BLOCK DIAGRAM
VAA
ADV7177
ONLY
OSD_EN
OSD_0
OSD_1
OSD_2
COLOR
DATA
P7–P0
P15–P8
HSYNC
FIELD/VSYNC
BLANK
ADV7177/ADV7178
8
4:2:2 TO
4:4:4 8
INTER-
POLATOR
8
8
YCrCb
TO 8
YUV
MATRIX
8
ADD 8
SYNC
ADD 8
BURST
ADD 8
BURST
INTER- 8
POLATOR
INTER- 8
POLATOR
INTER- 8
POLATOR
VIDEO TIMING
GENERATOR
I2C MPU PORT
YUV TO
RBG
MATRIX
Y
LOW-PASS
FILTER
U9
LOW-PASS
FILTER
V9
LOW-PASS
FILTER
9
99
SIN/COS
DDS BLOCK
9 9-BIT
DAC
9 9-BIT
DAC
9 9-BIT
DAC
DAC A
(PIN 31)
DAC B
(PIN 27)
DAC C
(PIN 26)
VOLTAGE
REFERENCE
CIRCUIT
VREF
RSET
COMP
CLOCK CLOCK CLOCK/2 RESET SCLOCK SDATA ALSB
GND
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.







ADV7178 pdf, 数据表
ADV7177/ADV7178
3.3 V DYNAMIC SPECIFICATIONS
VAA = 3.0 V to 3.6 V,1 VREF = 1.235 V, RSET = 300 Ω. All specifications TMIN to TMAX,2 unless otherwise noted.
Table 4.
Parameter
FILTER CHARACTERISTICS
Luma Bandwidth3 (Low-Pass Filter)
Stop-Band Cutoff
Pass-Band Cutoff, F3 dB
Chroma Bandwidth
Stop-Band Cutoff
Pass-Band Cutoff, F3 dB
Luma Bandwidth3 (Low-Pass Filter)
Stop-Band Cutoff
Pass-Band Cutoff, F3 dB
Chroma Bandwidth
Stop-Band Cutoff
Pass-Band Cutoff, F3 dB
Differential Gain4
Differential Phase4
SNR4 (Pedestal)
SNR4 (Ramp)
Hue Accuracy4
Color Saturation Accuracy4
Luminance Nonlinearity4
Chroma AM Noise4
Chroma PM Noise4
Chroma AM Noise4
Chroma PM Noise4
Conditions1
NTSC mode
>54 dB attenuation
>3 dB attenuation
NTSC mode
>40 dB attenuation
>3 dB attenuation
PAL mode
>50 dB attenuation
>3 dB attenuation
PAL mode
>40 dB attenuation
>3 dB attenuation
Normal power mode
Normal power mode
RMS
Peak periodic
RMS
Peak periodic
NTSC
NTSC
PAL
PAL
Min Typ Max Unit
7.0
4.2
3.2
2.0
7.4
5.0
4.0
2.4
1.0
1.0
70
64
56
54
1.2
1.4
1.4
64
62
64
62
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
Degrees
dB rms
dB p-p
dB rms
dB p-p
Degrees
%
±%
dB
dB
dB
dB
1 The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.
2 Temperature range TMIN to TMAX: 0°C to 70°C.
3 These specifications are for the low-pass filter only and are guaranteed by design. For other internal filters, see Table 7.
4 Guaranteed by characterization.
Rev. C | Page 8 of 44







ADV7178 equivalent, schematic
ADV7177/ADV7178
THEORY OF OPERATION
DATA PATH DESCRIPTION
For PAL B, D, G, H, I, M, N and NTSC M, N modes, YCrCb
4:2:2 data is input via the CCIR-656-compatible pixel port at
a 27 MHz data rate. The pixel data is demultiplexed to form
three data paths. Y typically has a range of 16 to 235, Cr and
Cb typically have a range of 128 ± 112; however, it is possible
to input data from 1 to 254 on both Y, Cb and Cr. The
ADV7177/ADV7178 support PAL (B, D, G, H, I, N, M) and
NTSC (with and without pedestal) standards. The appropriate
SYNC, BLANK, and burst levels are added to the YCrCb data.
Macrovision AntiTaping (ADV7178 only), closed captioning,
OSD (ADV7177 only), and teletext levels are also added to Y,
and the resulting data is interpolated to a rate of 27 MHz. The
interpolated data is filtered and scaled by three digital FIR
filters.
The U and V signals are modulated by the appropriate
subcarrier sine/cosine phases and added together to make up
the chrominance signal. The luma (Y) signal can be delayed
1 to 3 luma cycles (each cycle is 74 ns) with respect to the
chroma signal. The luma and chroma signals are then added
together to make up the composite video signal. All edges are
slew-rate limited.
The YCrCb data is also used to generate RGB data with
appropriate SYNC and BLANK levels. The RGB data is in
synchronization with the composite video output. Alternatively,
analog YUV data can be generated instead of RGB.
The three 9-bit DACs can be used to output:
RGB video
YUV video
One composite video signal + LUMA and CHROMA
(S-video).
Alternatively, each DAC can be individually powered off if not
required.
Video output levels are illustrated in the section NTSC
Waveforms With Pedestal.
Internal Filter Response
The Y filter supports several different frequency responses,
including two 4.5 MHz/5.0 MHz low-pass responses, PAL/
NTSC subcarrier notch responses, and a PAL/NTSC extended
response. The U and V filters have a 1.0 MHz/1.3 MHz low-
pass response for NTSC/PAL. These filter characteristics are
illustrated in the Typical Performance Characteristics section.
Color-Bar Generation
The devices can be configured to generate 100/7.5/75/7.5 color
bars for NTSC or 100/0/75/0 for PAL color bars. These are
enabled by setting MR17 of Mode Register 1 to Logic 1.
Square Pixel Mode
The ADV7177/ADV7178 can be used to operate in square pixel
mode. For NTSC operation, an input clock of 24.5454 MHz is
required. Alternatively, an input clock of 29.5 MHz is required
for PAL operation. The internal timing logic adjusts accordingly
for square pixel mode operation.
Color Signal Control
The color information can be switched on and off the video
output by using Bit MR24 of Mode Register 2.
Burst Signal Control
The burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
NTSC Pedestal Control
The pedestal on both odd and even fields can be controlled on a
line-by-line basis by using the NTSC pedestal control registers.
This allows the pedestals to be controlled during the vertical
blanking interval.
PIXEL TIMING DESCRIPTION
The ADV7177/ADV7178 can operate in either 8-bit or 16-bit
YCrCb mode.
8-Bit YCrCb Mode
This default mode accepts multiplexed YCrCb inputs through
the P7 to P0 pixel inputs. The inputs follow the sequence Cb0,
Y0 Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a
rising clock edge.
16-Bit YCrCb Mode
This mode accepts Y inputs through the P7 to P0 pixel inputs
and multiplexed CrCb inputs through the P15 to P8 pixel
inputs. The data is loaded on every second rising edge of
CLOCK. The inputs follow the sequence Cb0, Y0 Cr0,
Y1 Cb1, Y2, etc.
OSD
The ADV7177 supports OSD. There are twelve, 8-bit OSD
registers loaded with data from the four most significant bits of
Y, Cb, Cr input pixel data bytes. A choice of eight colors can,
therefore, be selected via the OSD_0, OSD_1, OSD_2 pins, each
color being a combination of 12 bits of Y, Cb, Cr pixel data. The
display is under control of the OSD_EN pin. The OSD window
can be an entire screen or just one pixel, and its size may change
by using the OSD_EN signal to control the width on a line-by-
line basis. Figure 5 illustrates OSD timing on the ADV7177.
Rev. C | Page 16 of 44










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