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PDF ( 数据手册 , 数据表 ) ADV7176

零件编号 ADV7176
描述 Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
制造商 Analog Devices
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ADV7176 数据手册, 描述, 功能
a
Integrated Digital CCIR-601
YCrCb to PAL/NTSC Video Encoder
ADV7175/ADV7176
FEATURES
Close Captioning Support
CCIR-601 YCrCb to PAL/NTSC Video Encoder
Teletext Support (Passthrough Mode)
Single 27 MHz Clock Required (؋2 Oversampling)
On-Board Color Bar Generation
Pixel Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Format
On-Board Voltage Reference
2-Wire Serial MPU Interface (I2C Compatible)
4:2:2 16-Bit Parallel Input Format
+5 V CMOS Monolithic Construction
SMPTE 170M NTSC Compatible Composite Video Output
44-Pin PQFP Thermally Enhanced Package
CCIR624/CCIR601 PAL Compatible Composite Video Output
SCART/PeriTV Support
YUV Output Mode
Simultaneous Composite and S-VHS Y/C or RGB YUV
Video Outputs
Programmable Luma Filters (Low-Pass/Notch)
Square Pixel Support (Slave Mode)
Allows Subcarrier Phase Locking with External Video
Source
APPLICATIONS
MPEG-1 and MPEG-2 Video
DVD
Digital Satellite/Cable Systems (Set Top Boxes/IRDs)
Video Games
CD Video/Karaoke
Professional Studio Quality
PC Video/Multimedia
10-Bit DAC Resolution for Encoded Video Channels
8-Bit DAC Resolution for RGB Output
YUV Interpolation for Accurate Subcarrier Construction
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Master/Slave Operation Supported
Master Mode Timing Programmability
Macrovision Antitaping Facility Rev 6.1/7.x (ADV7175 Only)*
GENERAL DESCRIPTION
The ADV7175/ADV7176 is an integrated digital video encoder
that converts Digital CCIR-601 4:2:2 component video data into a
standard analog baseband television signal compatible with world
wide standards NTSC, PAL B/D/G/H/I, PAL M or PAL N. In
addition to the composite output signal, there is the facility to out-
put S-VHS Y/C video, YUV or RGB video. The Y/C, YUV or
RGB format is simultaneously available at the analog outputs with
the composite video signal. Each analog output generates a
standard video-level signal into a doubly terminated 75 load.
(Continued on page 6)
FUNCTIONAL BLOCK DIAGRAM
VAA
RESET
COLOR
DATA
P7–P0
P15–P8
8
4:2:2 TO
4:4:4
INTER-
POLATOR
8
8
YCrCb
TO
YUV
MATRIX
HSYNC
FIELD/VSYNC
BLANK
VIDEO TIMING
GENERATOR
YUV TO
RBG
MATRIX
8
8
8
8
ADD 8
INTER-
8
Y 10
LOW-PASS
SYNC
POLATOR
FILTER
8
ADD 8
BURST
INTER- 8
POLATOR
U 10
LOW-PASS
FILTER
8 ADD 8
BURST
I2C MPU PORT
INTER- 8
POLATOR
V
LOW-PASS
FILTER
REAL-TIME
CONTROL
CIRCUIT
10
10 10
SIN/COS
DDS BLOCK
M
U 10
L
T
I
P
10
L
E
X 10
E
R
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10 10-BIT
DAC
ADV7175/ADV7176
VOLTAGE
REFERENCE
CIRCUIT
GREEN/
LUMA/
Y
RED/
CHROMA/
V
BLUE/
COMPOSITE/
U
COMPOSITE
VREF
RSET
COMP
CLOCK
SCLOCK SDATA ALSB
SCRESET/RTC
GND
*This device is protected by U.S. Patent Numbers 4631603, 4577216, 4819098 a nd other intellectual property rights. The Macrovision anticopy process is
licensed for noncommercial home use only, which is its sole intended use in the devic e. Please contact sales office for latest Macrovision version available.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703







ADV7176 pdf, 数据表
ADV7175/ADV7176
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0 2 4 6 8 10
FREQUENCY – MHz
Figure 10. NTSC UV Filter
12
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
2 4 6 8 10
FREQUENCY – MHz
Figure 11. PAL UV Filter
12
COLOR BAR GENERATION
The ADV7175/ADV7176 can be configured to generate 75%
amplitude, 75% saturation (75/7.5/75/7.5) for NTSC or 75%
amplitude, 100% saturation (100/0/75/0) for PAL color bars.
These are enabled by setting MR17 of Mode Register 1 to
Logic “1.”
SQUARE PIXEL MODE
The ADV7175/ADV7176 can be used to operate in square
pixel mode. For NTSC operation an input clock of 24.54 MHz
is required. Alternatively, for PAL operation, an input clock of
29.5 MHz is required. The internal filters scale accordingly for
square pixel mode operation.
COLOR SIGNAL CONTROL
The color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
BURST SIGNAL CONTROL
The burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
NTSC PEDESTAL CONTROL
The pedestal information on both odd and even fields can be
controlled on a line by line basis using the NTSC Pedestal
Control Registers. This allows the pedestals to be controlled
during the vertical blanking interval (Lines 10 to 25).
SUBCARRIER RESET
Together with the SCRESET/RTC PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175/ADV7176 can be
used in subcarrier reset mode. The subcarrier will reset to field
0 at the start of the following field when a high to low transition
occurs on this input pin.
REAL TIME CONTROL
Together with the SCRESET/RTC PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175/ADV7176 can be
used to lock an external video source. The real time control
mode allows the ADV7175/ADV7176 to automatically alter the
subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs out a digi-
tal datastream in the RTC format (such as a Phillips SAA7110
video decoder), the part will automatically change to the com-
pensated subcarrier frequency on a line by line basis. This
digital datastream is 67 bits wide and the subcarrier is con-
tained in bits 0 to 21. Each bit is 2 clock cycles long.
COMPOSITE
VIDEO
e.g. VCR
OR CABLE
VIDEO
DECODER
(e.g.SAA7110)
MPEG
DECODER
M
U
X
CLOCK
SCRESET/RTC
GREEN/LUMA/Y
P7–P0
RED/CHROMA/V
BLUE/COMPOSITE/U
HSYNC
COMPOSITE
FIELD/VSYNC
ADV7175/ADV7176
Figure 12. RTC Connections
PIXEL TIMING DESCRIPTION
The ADV7175/ADV7176 can operate in either 8-bit or 16-bit
YCrCb Mode.
8-Bit YCrCb Mode
This default mode accepts multiplexed YCrCb inputs through
the P7–P0 pixel inputs. The inputs follow the sequence Cb0,
Y0 Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on
a rising clock edge.
16-Bit YCrCb Mode
This mode accepts Y inputs through the P7-P0 pixel inputs and
multiplexed CrCb inputs through the P15-P8 pixel inputs. The
data is loaded on every second rising clock edge of CLOCK.
The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.
VIDEO TIMING DESCRIPTION
The ADV7175/ADV7176 is intended to interface to off the shelf
MPEG1 and MPEG2 Decoders. As a consequence the
ADV7175/ADV7176 accepts 4:2:2 YCrCb pixel data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing gen-
erator. The ADV7175/ADV7176 generates all of the required
horizontal and vertical timing periods and levels for the analog
video outputs.
The ADV7175/ADV7176 calculates the width and placement
of analog sync pulses, blanking levels and color burst envelopes.
Color bursts are disabled on appropriate lines and serration and
equalization pulses are inserted where required.
(Continued on page 15)
–8– REV. A







ADV7176 equivalent, schematic
ADV7175/ADV7176
MPU PORT DESCRIPTION
The ADV7175 and ADV7176 support a two wire serial (I2C
compatible) microprocessor bus driving multiple peripherals.
Two inputs serial data (SDATA) and serial clock (SCLOCK)
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. The
ADV7175 and ADV7176 each have four possible slave ad-
dresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 26 and
Figure 27. The LSB sets either a read or write operation.
Logic Level “1” corresponds to a read operation while Logic
Level “0” corresponds to a write operation. A1 is set by setting
the ALSB pin of the ADV7175/ADV7176 to Logic Level “0” or
Logic Level “1.”
1 1 0 1 0 1 A1 X
ADDRESS
CONTROL
SET UP BY
ALSB
READ / W RITE
CONTROL
0 WRITE
1 READ
Fig 26. ADV7175 Slave Address
0 1 0 1 0 1 A1 X
ADDRESS
CONTROL
SET UP BY
ALSB
READ / W RITE
CONTROL
0 WRITE
1 READ
Fig 27. ADV7176 Slave Address
To control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by es-
tablishing a start condition, defined by a high to low transition
on SDATA while SCLOCK remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address +
R/W bit). The bits transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDATA and SCLOCK
lines waiting for the Start condition and the correct transmitted
address. The R/W bit determines the direction of the data. A
Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the
LSB of the first byte means that the master will read informa-
tion from the peripheral.
The ADV7175/ADV7176 acts as a standard slave device on the
bus. The data on the SDATA pin is 8 bits long supporting the
7-bit addresses plus the R/W bit. The ADV7175 has 33 sub-
addresses and the ADV7176 has 19 subaddresses to enable ac-
cess to the internal registers. It, therefore, interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses auto increment allowing data to
be written to or from the starting subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one by one basis without
having to update all the registers. There is one exception. The
Subcarrier Frequency Registers should be updated in sequence,
starting with Subcarrier Frequency Register 0. The auto incre-
ment function should be then used to increment and access
subcarrier frequency registers 1, 2 and 3. The subcarrier fre-
quency registers should not be accessed independently.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of se-
quence with normal read and write operations, then these cause
an immediate jump to the idle condition. During a given
SCLOCK high period the user should only issue one start con-
dition, one stop condition or a single stop condition followed by
a single start condition. If an invalid subaddress is issued by the
user, the ADV7175/ADV7176 will not issue an acknowledge
and will return to the idle condition. If in auto-increment
mode, the user exceeds the highest subaddress then the follow-
ing action will be taken:
1. In Read Mode the highest subaddress register contents will
continue to be output until the master device issues a no-ac-
knowledge. This indicates the end of a read. A no-acknowledge
condition is where the SDATA line is not pulled low on the
ninth pulse.
2. In Write Mode, the data for the invalid byte will be not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7175/ADV7176 and the part will re-
turn to the idle condition.
Figure 28 illustrates an example of data transfer for a read se-
quence and the start and stop conditions.
SDATA
SCLOCK S
1-7 8 9
1-7 8 9
START ADDR R/W ACK SUBADDRESS ACK
1-7 8
DATA
9
ACK
P
STOP
Figure 28. Bus Data Transfer
Figure 29 shows bus write and read sequences.
WRITE
SEQUENCE
S SLAVE ADDR A(S)
SUB ADDR
A(S)
LSB = 0
DATA
A(S)
LSB = 1
DATA
A(S) P
READ
SEQUENCE
S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S)
DATA
A(M)
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
DATA
A(M) P
Figure 29. Write and Read Sequences
–16–
REV. A










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