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PDF ( 数据手册 , 数据表 ) DT28F800F3

零件编号 DT28F800F3
描述 FAST BOOT BLOCK FLASH MEMORY
制造商 Intel
LOGO Intel LOGO 


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DT28F800F3 数据手册, 描述, 功能
E
PRODUCT PREVIEW
FAST BOOT BLOCK
FLASH MEMORY FAMILY
8 AND 16 MBIT
28F800F3, 28F160F3
Includes Extended and Automotive Temperature Specifications
n High Performance
54 MHz Effective Zero Wait-State
Performance
Synchronous Burst-Mode Reads
Asynchronous Page-Mode Reads
n SmartVoltage Technology
2.7 V3.6 V Read and Write
Operations for Low Power Designs
12 V VPP Fast Factory Programming
n Flexible I/O Voltage
1.65 V I/O Reduces Overall System
Power Consumption
5 V-Safe I/O Enables Interfacing to
5 V Devices
n Enhanced Data Protection
Absolute Write Protection with
VPP = GND
Block Locking
Block Erase/Program Lockout
during Power Transitions
n Density Upgrade Path
8- and 16-Mbit
n Manufactured on ETOX™ V Flash
Technology
n Supports Code Plus Data Storage
Optimized for Flash Data Integrator
(FDI) Software
Fast Program Suspend Capability
Fast Erase Suspend Capability
n Flexible Blocking Architecture
Eight 4-Kword Blocks for Data
32-Kword Main Blocks for Code
Top or Bottom Configurations
Available
n Extended Cycling Capability
Minimum 10,000 Block Erase Cycles
Guaranteed
n Low Power Consumption
Automatic Power Savings Mode
Decreases Power Consumption
n Automated Program and Block Erase
Algorithms
Command User Interface for
Automation
Status Register for System
Feedback
n Industry-Standard Packaging
56-Lead SSOP
µBGA* CSP
Intel’s Fast Boot Block memory family renders high performance asynchronous page-mode and synchronous
burst reads making it an ideal memory solution for burst CPUs. Combining high read performance with the
intrinsic non-volatility of flash memory, this flash memory family eliminates the traditional redundant memory
paradigm of shadowing code from a slow nonvolatile storage source to a faster execution memory for
improved system performance. Therefore, it reduces the total memory requirement which helps increase
reliability and reduce overall system power consumption and cost.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They are available
in industry-standard packages: the µBGA* CSP, ideal for board-constrained applications, and the rugged
56-lead SSOP.
May 1998
Order Number: 290644-001







DT28F800F3 pdf, 数据表
FAST BOOT BLOCK DATASHEET
E
Sym
A0–A19
DQ0
DQ15
CLK
ADV#
CE#
RST#
OE#
WE#
WP#
WAIT#
Table 1. Pin Descriptions
Type
Name and Function
INPUT ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during read and write cycles.
8-Mbit: A0–18, 16-Mbit: A0–19
INPUT/
OUTPUT
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles, outputs
data during memory array, status register (DQ0–DQ7), and identifier code read
cycles. Data pins float to high-impedance when the chip is deselected or outputs
are disabled. Data is internally latched during a write cycle.
INPUT
CLOCK: Synchronizes the flash memory to the system operating frequency during
synchronous burst-mode read operations. When configured for synchronous burst-
mode reads, address is latched on the first rising (or falling, depending upon the
read configuration register setting) CLK edge when ADV# is active or upon a rising
ADV# edge, whichever occurs first. CLK is ignored during asynchronous page-
mode read and write operations.
INPUT
ADDRESS VALID: Indicates that a valid address is present on the address inputs.
Addresses are latched on the rising edge of ADV# during read and write
operations. ADV# may be tied active during asynchronous read and write
operations.
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. CE#-high deselects the device and reduces power consumption
to standby levels.
INPUT
RESET: When driven low, RST# inhibits write operations which provides data
protection during power transitions, and it resets internal automation. RST#-high
enables normal operation. Exit from reset sets the device to asynchronous read
array mode.
INPUT OUTPUT ENABLE: Gates data outputs during a read cycle.
INPUT WRITE ENABLE: Controls writes to the CUI and array. Addresses and data are
latched on the rising edge of the WE# pulse.
INPUT WRITE PROTECTION: Provides a method for locking and unlocking all main
blocks and two parameter blocks.
When WP# is at logic low, lockable blocks are locked. If a program or erase
operation is attempted on a locked block, SR.1 and either SR.4 [program] or SR.5
[block erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked and can be
programmed or erased.
OUTPUT
WAIT: Provides data valid feedback when configured for synchronous burst-mode
and the burst length is set to continuous. This signal is gated by OE# and CE# and
is internally pull-up to VCCQ via a resistor. WAIT# from several components can be
tied together to form one system WAIT# signal.
8 PRODUCT PREVIEW







DT28F800F3 equivalent, schematic
FAST BOOT BLOCK DATASHEET
E
WSMS
ESS
Table 5. Status Register Definition
ES
PS
VPPS
PSS
DPS
R
76543210
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Check SR.7 to determine block erase or program
completion. SR.6–0 are invalid while SR.7 = “0.”
SR.6 = ERASE SUSPEND STATUS (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
When an Erase Suspend command is issued, the
WSM halts execution and sets both SR.7 and SR.6
to “1.” SR.6 remains set until an Erase Resume
command is written to the CUI.
SR.5 = ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
If both SR.5 and SR.4 are “1”s after a block erase or
program attempt, an improper command sequence
was entered.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Program
0 = Successful Program
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.3 does not provide a continuous VPP feedback.
The WSM interrogates and indicates the VPP level
only after a block erase or program operation. SR.3
is not guaranteed to reports accurate feedback
when VPP VPPH1/2 or VPPLK.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When an Program Suspend command is issued, the
WSM halts execution and sets both SR.7 and SR.2
to “1.” SR.2 remains set until an Program Resume
command is written to the CUI.
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Block Erase or Program Attempted on a
Locked Block, Operation Abort
0 = Unlocked
If a block erase or program operation is attempted to
a locked block, SR.1 is set by the WSM and aborts
the operation if WP# = VIL.
SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
SR.0 is reserved for future use and should be
masked out when polling the status register.
16 PRODUCT PREVIEW










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