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PDF ( 数据手册 , 数据表 ) DT28F320S3

零件编号 DT28F320S3
描述 WORD-WIDE FlashFile MEMORY
制造商 Intel
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DT28F320S3 数据手册, 描述, 功能
E
ADVANCE INFORMATION
WORD-WIDE
FlashFile™ MEMORY FAMILY
28F160S3, 28F320S3
Includes Extended Temperature Specifications
n Two 32-Byte Write Buffers
2.7 µs per Byte Effective
Programming Time
n Low Voltage Operation
2.7V or 3.3V VCC
2.7V, 3.3V or 5V VPP
n 100 ns Read Access Time (16 Mbit)
110 ns Read Access Time (32 Mbit)
n High-Density Symmetrically-Blocked
Architecture
32 64-Kbyte Erase Blocks (16 Mbit)
64 64-Kbyte Erase Blocks (32 Mbit)
n System Performance Enhancements
STS Status Output
n Industry-Standard Packaging
µBGA* package, SSOP, and
TSOP (16 Mbit)
µBGA* package and SSOP (32 Mbit)
n Cross-Compatible Command Support
Intel Standard Command Set
Common Flash Interface (CFI)
Scaleable Command Set (SCS)
n 100,000 Block Erase Cycles
n Enhanced Data Protection Features
Absolute Protection with VPP = GND
Flexible Block Locking
Block Erase/Program Lockout
during Power Transitions
n Configurable x8 or x16 I/O
n Automation Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n ETOX™ V Nonvolatile Flash
Technology
Intel’s Word-Wide FlashFile™ memory family provides high-density, low-cost, non-volatile, read/write storage
solutions for a wide range of applications. The Word-Wide FlashFile memories are available at various
densities in the same package type. Their symmetrically-blocked architecture, flexible voltage, and extended
cycling provide highly flexible components suitable for resident flash arrays, SIMMs, and memory cards.
Enhanced suspend capabilities provide an ideal solution for code or data storage applications. For secure
code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the Word-Wide FlashFile memories offer three levels of protection: absolute protection
with VPP at GND, selective block locking, and program/erase lockout during power transitions. These
alternatives give designers ultimate control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. It comes in the
industry-standard 56-lead SSOP and µBGA packages. In addition, the 16-Mb device is available in the
industry-standard 56-lead TSOP package.
June 1997
Order Number: 290608-001







DT28F320S3 pdf, 数据表
28F160S3, 28F320S3
28F016SA 28F160S3
28F016SV 28F160S5
3/5#
CE1#
NC
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0#
VPP
RP#
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
NC
CE1#
NC
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0#
VPP
RP#
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56-LEAD TSOP
STANDARD PINOUT
14 mm x 20 mm
TOP VIEW
Highlights pinout changes.
Figure 2. TSOP 56-Lead Pinout
E
28F160S3 28F016SA
28F160S5 28F016SV
56 WP# WP#
55 WE# WE#
54 OE# OE#
53 STS RRYY//BBYY##
52
DQ15
DQ15
51
DQ7
DQ7
50
DQ14
DQ14
49
DQ6
DQ6
48 GND GND
47
DQ13
DQ13
46
DQ5
DQ5
45
DQ12
DQ12
44
DQ4
DQ4
43
VCC
VCC
42 GND GND
41
DQ11
DQ11
40
DQ3
DQ3
39
DQ10
DQ10
38
DQ2
DQ2
37
VCC
VCC
36
DQ9
DQ9
35
DQ1
DQ1
34
DQ8
DQ8
33
DQ0
DQ0
32 A0 A0
31 BYTE# BYTE#
30 NC NC
29 NC NC
8 ADVANCE INFORMATION







DT28F320S3 equivalent, schematic
28F160S3, 28F320S3
E
NOTES:
1. Bus operations are defined in Table 2.
2. X = Any valid address within the device.
BA = Address within the block being erased or locked.
IA = Identifier Code Address: see Table 12.
QA = Query database Address.
PA = Address of memory location to be programmed.
3. ID = Data read from Query database.
SRD = Data read from Status Register. See Table 15 for a description of the Status Register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
CC = Configuration Code. (See Table 14.)
4. The upper byte of the data bus (DQ8–15) during command writes is a “Don’t Care” in x16 operation.
5. Following the Read Identifier Codes command, read operations access manufacturer, device, and block-lock codes. See
Section 4.3 for read identifier code data.
6. If a block is locked (i.e., the block’s lock-bit is set to 0), WP# must be at VIH in order to perform block erase, program and
suspend operations. Attempts to issue a block erase, program and suspend operation to a locked block while WP# is VIL
will fail.
7. Either 40H or 10H are recognized by the WSM as the byte/word program setup.
8. After the Write to Buffer command is issued, check the XSR to make sure a Write Buffer is available.
9. N = byte/word count argument such that the number of bytes/words to be written to the input buffer = N + 1. N = 0 is 1
byte/word length, and so on. Write to Buffer is a multi-cycle operation, where a byte/word count of N + 1 is written to the
correct memory address (WA) with the proper data (WD). The Confirm command (D0h) is expected after exactly N + 1 write
cycles; any other command at that point in the sequence aborts the buffered write. Writing a byte/word count outside the
buffer boundary causes unexpected results and should be avoided.
10. The write to buffer, block erase, or full chip erase operation does not begin until a Confirm command (D0h) is issued.
Confirm also reactivates suspended operations.
11. A block lock-bit can be set only while WP# is VIH.
12. WP# must be at VIH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits.
13. Commands other than those shown above are reserved for future use and should not be used.
14. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The
Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.
16 ADVANCE INFORMATION










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