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零件编号 | K6F4016R4G-F | ||
描述 | 256K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM | ||
制造商 | Samsung semiconductor | ||
LOGO | |||
1 Page
K6F4016R4G Family
Preliminary
CMOS SRAM
Document Title
www.DataSheet4U.com
256K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
0.0 Initial draft
Draft Date
Remark
November 14, 2003 Preliminary
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
- 1 - Revision 0.0
November 2003
K6F4016R4G Family
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
Address
CS
UB, LB
WE
Data in
tAS(3)
tWC
tCW(2)
tAW
tBW
tWP(1)
tWR(4)
tDW tDH
Data Valid
Preliminary
CMOS SRAM
www.DataSheet4U.com
Data out
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS or LB/UB controlled
VCC
1.65V
tSDR
1.4V
VDR
CS or LB/UB
GND
Data Retention Mode
CS≥VCC-0.2V or LB=UB≥Vcc-0.2V
tRDR
- 8 - Revision 0.0
November 2003
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页数 | 9 页 | ||
下载 | [ K6F4016R4G-F.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
K6F4016R4G-F | 256K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM | Samsung semiconductor |
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