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PDF ( 数据手册 , 数据表 ) W83627UHG

零件编号 W83627UHG
描述 LPC I/O
制造商 nuvoton
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W83627UHG 数据手册, 描述, 功能
W83627UHG
NCT6627UD
NUVOTON LPC I/O
Date: October 26th, 2010 Revision: 1.7
Publication Release Date: October 26, 2010
-I- Revision 1.7







W83627UHG pdf, 数据表
List of Figures
Figure 3-1 W83627UHG Block Diagram ........................................................................................... 6
Figure 4-1 W83627UHG Pin Layout ................................................................................................. 7
Figure 6-1 Structure of the Configuration Register ......................................................................... 22
Figure 6-2 Configuration Register ................................................................................................... 24
Figure 7-1 LPC Bus’ Reads from / Writes to Internal Registers...................................................... 29
Figure 7-2 Serial Bus Write to Internal Address Register Followed by the Data Byte .................... 30
Figure 7-3 Serial Bus Read from Internal Address Register........................................................... 31
Figure 7-4 Analog Inputs and Application Circuit of the W83627UHG ........................................... 32
Figure 7-5 Monitoring Temperature from Thermistor...................................................................... 35
Figure 7-6 Monitoring Temperature from Thermal Diode (Voltage Mode)...................................... 35
Figure 7-7 Monitoring Temperature from Thermal Diode ............................................................... 36
Figure 7-8 PECI Illustration ............................................................................................................. 41
Figure 7-9 FANOUT and Corresponding Temperature Sensors in SMART FANTMI ...................... 44
Figure 7-10 Mechanism of Thermal CruiseTM Mode (PWM Duty Cycle) ........................................ 45
Figure 7-11 Mechanism of Thermal CruiseTM Mode (DC Output Voltage) ..................................... 45
Figure 7-12 Mechanism of Fan Speed CruiseTM Mode................................................................... 46
Figure 7-13 FANOUT and Corresponding Temperature Sensor in SMART FANTM III ................... 48
Figure 7-14 Setting of SMART FANTM III......................................................................................... 48
Figure 7-15 SMART FANTM III Mechanism (Current Temp. > Target Temp. + Tol.)....................... 49
Figure 7-16 SMART FANTM III Mechanism (Current Temp. < Target Temp. – Tol.)....................... 50
Figure 7-17 SMI Mode of Voltage and Fan Inputs .......................................................................... 52
Figure 7-18 SMI Mode of SYSTIN I ................................................................................................ 53
Figure 7-19 SMI Mode of SYSTIN II ............................................................................................... 54
Figure 7-20 SMI Mode of CPUTIN .................................................................................................. 54
Figure 7-21 OVT# Modes of Temperature Inputs ........................................................................... 55
Figure 7-22 Caseopen Mechanism ................................................................................................. 56
Figure 12-1 Keyboard and Mouse Interface.................................................................................. 137
Figure 13-1 Power Control Mechanism......................................................................................... 144
Figure 13-2 Power Sequence from S5 to S0, then back to S5. .................................................... 145
Figure 13-3 Mechanism of Resume Reset Logic.......................................................................... 148
Figure 14-1 Start Frame Timing with Source Sampled A Low Pulse on IRQ1 ............................. 151
Figure 14-2 Stop Frame Timing with Host Using 17 SERIRQ Sampling Period........................... 153
-VIII-
Publication Release Date: October 26, 2010
Revision 1.7







W83627UHG equivalent, schematic
4. PIN LAYOUT
W83627UHG/NCT6627UD
CPUTIN
SYSTIN
AGND
GP22
GP21/BEEP
GP20/PLED
CTSC#/GP37
DSRC#/GP36
RTSC#/GP35
DTRC#/GP34
SINC/GP33
SOUTC/GP32
DCDC#/GP31
RIC#/GP30
CTSD#/GP47
DSRD#/GP46
(FAN_SET) RTSD#/GP45
DTRD#/GP44
SIND/GP43
(GPI_MUL) SOUTD/GP42
DCDD#/GP41
RID#/GP40
CTSE#/GP57
DSRE#/GP56
RTSE#/GP55
DTRE#/GP54
103
104
105
AVCC
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
5VCC Vtt
VSB
VBAT
W83627UHG
5VCC
VSB
64 SUSLED
63 KDAT
62 KCLK
61 5VSB
60 GP27
59 KBRST#
58 GA20M
57 RIA#
56 DCDA#
55 VSS
54 SOUTA(PENKBC)
53 SINA
52 DTRA# (PFDCUART)
51 RTSA# (HEFRAS)
50 DSRA#
49 CTSA#
48 5VCC
47 STB#
46 AFD#
45 ERR#
44 INIT#
43 SLIN#
42 PD0
41 PD1
40 PD2
39 PD3
Figure 4-1 W83627UHG Pin Layout
Publication Release Date: October 26, 2010
-7- Revision 1.7










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