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PDF ( 数据手册 , 数据表 ) W77C32

零件编号 W77C32
描述 8-BIT MICROCONTROLLER
制造商 nuvoton
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W77C32 数据手册, 描述, 功能
W77C32/W77C032A Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION .......................................................................................................... 3
2. FEATURES.................................................................................................................................. 3
3. PIN CONFIGURATIONS ............................................................................................................. 4
4. PIN DESCRIPTION ..................................................................................................................... 5
5. FUNCTIONAL DESCRIPTION .................................................................................................... 6
6. MEMORY ORGANIZATION ........................................................................................................ 8
6.1 Program Memory............................................................................................................. 8
6.2 Data Memory ................................................................................................................... 8
7. SPECIAL FUNCTION REGISTERS .......................................................................................... 10
7.1 External Interrupt Flag ................................................................................................... 16
7.2 Timer 2 Mode Control.................................................................................................... 23
7.2.1
Timer 2 Capture LSB ..............................................................................................24
8. INSTRUCTION .......................................................................................................................... 27
8.1 Instruction Timing .......................................................................................................... 34
8.2 MOVX Instruction .......................................................................................................... 36
8.3 External Data Memory Access Timing .......................................................................... 38
8.4 Wait State Control Signal .............................................................................................. 40
9. POWER MANAGEMENT .......................................................................................................... 42
9.1 Idle Mode....................................................................................................................... 42
9.2 Economy Mode.............................................................................................................. 42
9.3 Power Down Mode ........................................................................................................ 43
10. RESET CONDITIONS ............................................................................................................... 45
10.1 External Reset ............................................................................................................... 45
10.2 Watchdog Timer Reset ................................................................................................. 45
10.3 Reset State.................................................................................................................... 45
11. INTERRUPTS............................................................................................................................ 47
11.1 Interrupt Sources ........................................................................................................... 47
11.2 Priority Level Structure .................................................................................................. 48
11.3 Interrupt Response Time............................................................................................... 49
12. PROGRAMMABLE TIMERS/COUNTERS ................................................................................ 51
12.1
Timer/Counters 0 & 1 .................................................................................................... 51
12.1.1
Time-base Selection ...............................................................................................51
12.1.2
Mode 0 ....................................................................................................................52
Publication Release Date: February 1, 2007
- 1 - Revision A8







W77C32 pdf, 数据表
W77C32/W77C032A
6. MEMORY ORGANIZATION
The W77C032 separates the memory into two separate sections, the Program Memory and the Data
Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory is
used to store data or for memory mapped devices.
6.1 Program Memory
The Program Memory on the W77C032 can be up to 64Kbytes long. All instructions are fetched for
execution from this memory area. The MOVC instruction can also access this memory region.
6.2 Data Memory
The W77C032 can access up to 64Kbytes of external Data Memory. This memory region is accessed
by the MOVX instructions. Unlike the 8051 derivatives, the W77C032 contains on-chip 1K bytes MOVX
SRAM of Data Memory, which can only be accessed by MOVX instructions. These 1K bytes of SRAM
are between address 0000H and 03FFH. Access to the on-chip MOVX SRAM is optional under
software control. When enabled by software, any MOVX instruction that uses this area will go to the on-
chip RAM. MOVX addresses greater than 03FFH automatically go to external memory through Port 0
and 2. When disabled, the 1KB memory area is transparent to the system memory map. Any MOVX
directed to the space between 0000H and FFFFH goes to the expanded bus on Port 0 and 2. This is
the default condition. In addition, the W77C032 has the standard 256 bytes of on-chip Scratchpad
RAM. This can be accessed either by direct addressing or by indirect addressing. There are also some
Special Function Registers (SFRs), which can only be accessed by direct addressing. Since the
Scratchpad RAM is only 256 bytes, it can be used only when data contents are small. In the event that
larger data contents are present, two selections can be used. One is on-chip MOVX SRAM, the other is
the external Data Memory. The on-chip MOVX SRAM can only be accessed by a MOVX instruction,
the same as that for external Data Memory. However, the on-chip RAM has the fastest access times.
FFh
80h
7Fh
00h
Indirect
Addressing
RAM
Direct &
Indirect
Addressing
RAM
SFRs
Direct
Addressing
only
FFFFh
64 K
Bytes
External
Data
Memory
FFFFh
64K bytes
of
External
Program
Memory
03FFh
0000h
1K Bytes
On-chip SRAM
0000h
Figure 1. Memory Map
0000h
-8-







W77C32 equivalent, schematic
W77C32/W77C032A
7.1 External Interrupt Flag
Bit: 7 6 5 4 3
2 10
IE5 IE4 IE3 IE2 XT/RG RGMD RGSL BGS
Mnemonic: EXIF
Address: 91h
IE5: External Interrupt 5 flag. Set by hardware when a falling edge is detected on INT5 .
IE4: External Interrupt 4 flag. Set by hardware when a rising edge is detected on INT4.
IE3: External Interrupt 3 flag. Set by hardware when a falling edge is detected on INT5 .
IE2: External Interrupt 2 flag. Set by hardware when a rising edge is detected on INT2.
XT/ RG RG: Crystal/RC Oscillator Select. Setting this bit selects crystal or external clock as system
clock source. Clearing this bit selects the on-chip RC oscillator as clock source.
XTUP(STATUS.4) must be set to 1 and XTOFF (PMR.3) must be cleared before this bit can
be set. Attempts to set this bit without obeying these conditions will be ignored. This bit is set to
1 after a power-on reset and unchanged by other forms of reset.
RGMD: RC Mode Status. This bit indicates the current clock source of microcontroller. When cleared,
CPU is operating from the external crystal or oscillator. When set, CPU is operating from the
on-chip RC oscillator. This bit is cleared to 0 after a power-on reset and unchanged by other
forms of reset.
RGSL: RC Oscillator Select. This bit selects the clock source following a resume from Power Down
Mode. Setting this bit allows device operating from RC oscillator when a resume from Power
Down Mode. When this bit is cleared, the device will hold operation until the crystal oscillator
has warmed-up following a resume from Power Down Mode. This bit is cleared to 0 after a
power-on reset and unchanged by other forms of reset.
Serial Port Control
Bit: 7
65432
SM0/FE SM1 SM2 REN TB8 RB8
1
TI
0
RI
Mnemonic: SCON
Address: 98h
SM0/FE: Serial port 0, Mode 0 bit or Framing Error Flag: The SMOD0 bit in PCON SFR determines
whether this bit acts as SM0 or as FE. The operation of SM0 is described below. When used
as FE, this bit will be set to indicate an invalid stop bit. This bit must be manually cleared in
software to clear the FE condition.
SM1: Serial port Mode bit 1:
SM0 SM1 Mode Description
0 0 0 Synchronous
0 1 1 Asynchronous
1 0 2 Asynchronous
1 1 3 Asynchronous
Length
8
10
11
11
Baud rate
4/12 Tclk
variable
64/32 Tclk
variable
- 16 -










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