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PDF ( 数据手册 , 数据表 ) M0516LDN

零件编号 M0516LDN
描述 32-BIT MICROCONTROLLER
制造商 nuvoton
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M0516LDN 数据手册, 描述, 功能
M051 DN/DE
ARM® Cortex® -M0
32-bit Microcontroller
NuMicro® Family
M051 DN/DE Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Oct. 05, 2015
Page 1 of 86
Rev 1.03







M0516LDN pdf, 数据表
M051 DN/DE
2 FEATURES
Core
ARM® Cortex® -M0 core running up to 50 MHz
One 24-bit system timer
Supports Low Power Sleep mode
A single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Supports Serial Wire Debug (SWD) interface and two watchpoints/four breakpoints
Provides hardware divider and supports signed 32-bit dividend, 16-bit divisor operation
Wide Operating Voltage Range: 2.5V to 5.5V
Memory
8KB/16KB/32KB/64KB Flash for program memory (APROM)
4KB Flash for data memory (Data Flash)
4KB Flash for loader (LDROM)
4KB SRAM for internal scratch-pad RAM (SRAM)
Clock Control
Programmable system clock source
22.1184 MHz internal oscillator
4~24 MHz external crystal input
10 kHz low-power oscillator for Watchdog Timer and wake-up in Sleep mode
PLL allows CPU operation up to the maximum 50 MHz
I/O Port
Up to 40 general-purpose I/O (GPIO) pins for LQFP-48 package
Four I/O modes:
Quasi-bidirectional
Push-Pull output
Open-Drain output
Input only with high impendence
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Supports high driver and high sink I/O mode
Configurable I/O mode after POR
Timer
Provides four channel 32-bit timers; one 8-bit pre-scale counter with 24-bit up-timer for
each timer
Independent clock source for each timer
24-bit timer value is readable through TDR (Timer Data Register)
Provides One-shot, Periodic and Toggle operation modes
Provides event counter function
Provides external capture/reset counter function
Two more timer clock sources from external trigger and internal 10 kHz
TIMER wake-up function
External capture input source selected from ACMP or TxEX
Toggle mode output pins selected from TxEX or TMx
Inter-Timer trigger mode
WDT (Watchdog Timer)
Oct. 05, 2015
Page 8 of 86
Rev 1.03







M0516LDN equivalent, schematic
M051 DN/DE
M0 5X - X X X
CPU core
ARM Cortex M0
Part Number
52: 08 KB Flash ROM
54: 16 KB Flash ROM
58: 32 KB Flash ROM
516: 64 KB Flash ROM
Package
: LQFP48
: QFN33
Temperature
N: - 40~ +85
E: - 40~ +105
Reserved
Figure 4-1 NuMicro® M051 DN/DE Series Naming Rule
Oct. 05, 2015
Page 16 of 86
Rev 1.03










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