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PDF ( 数据手册 , 数据表 ) M0564VG4AE

零件编号 M0564VG4AE
描述 32-BIT MICROCONTROLLER
制造商 nuvoton
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M0564VG4AE 数据手册, 描述, 功能
M0564
ARM CORTEX® -M
32-BIT MICROCONTROLLER
NuMicro® Family
M0564 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
May 05, 2017
Page 1 of 161
Rev 1.00







M0564VG4AE pdf, 数据表
M0564
List of Tables
Table 1.1-1 Key Features Support Table ....................................................................................... 10
Table 3.1-1 List of Abbreviations.................................................................................................... 20
Table 4.3-1 M0564 GPIO Multi-function Table .............................................................................. 54
Table 6.2-1 Reset Value of Registers ............................................................................................ 61
Table 6.2-2 Power Mode Difference Table .................................................................................... 65
Table 6.2-3 Clocks in Power Modes ............................................................................................. 67
Table 6.2-4 Condition of Entering Power-down Mode Again ......................................................... 68
Table 6.2-5 Address Space Assignments for On-Chip Controllers................................................ 71
Table 6.2-6 Exception Model ......................................................................................................... 78
Table 6.2-7 Interrupt Number Table............................................................................................... 79
Table 6.3-8 Clock Stable Count Value Table ................................................................................. 82
Table 6.17-30 PWM Pulse Generation Event Priority in Up Count Type..................................... 114
Table 6.17-31 PWM Pulse Generation Event Priority in Down Count Type ................................ 114
Table 6.17-32 PWM Pulse Generation Event Priority in Up-Down Count Type .......................... 114
May 05, 2017
Page 8 of 161
Rev 1.00







M0564VG4AE equivalent, schematic
M0564
SPI Mode
I2S Mode
SPI_CLK
I2S_BCLK
SPI_SS
SPI_MOSI
I2S_LRCLK
I2S_DO
SPI_MISO
I2S_DI
- I2S_MCLK
I2C
SPI Mode
Supports Master or Slave mode operation
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 4-/8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports Byte Reorder function
Supports PDMA transfer
I2S Mode
Supports Master or Slave mode operation
Capable of handling 8-, 16-, 24- and 32-bit word sizes in I2S mode
Provides separate 4-level depth transmit and receive FIFO buffers in I2S mode
Supports monaural and stereo audio data in I2S mode
Supports PCM mode A, PCM mode B, I2S and MSB justified data format in I2S
mode
Supports PDMA transfer
Supports up to two sets of I2C device
Supports Master/Slave mode
Supports bidirectional data transfer between masters and slaves
Supports multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
Supports 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up
and timer-out counter overflows
Programmable clocks allow versatile rate control
Supports multiple address recognition, four slave address with mask option
Supports two-level buffer function
Supports setup/hold time programmable
Supports wake-up function
ADC
Supports 12-bit SAR ADC
12-bit resolution and 10-bit accuracy is guaranteed
Analog input voltage range: 0~ AVDD
Supports external VREF pin
Up to 20 single-end analog input channels
Maximum ADC peripheral clock frequency is 16 MHz
Conversion rate up to 800K SPS at 5V
Configurable ADC internal sampling time
Supports single-scan, single-cycle-scan, and continuous scan and scan on enabled
channels
Supports individual conversion result register with valid and overrun indicators for each
May 05, 2017
Page 16 of 161
Rev 1.00










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