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PDF ( 数据手册 , 数据表 ) MPC9772

零件编号 MPC9772
描述 3.3V 1:12 LVCMOS PLL Clock Generator
制造商 IDT
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MPC9772 数据手册, 描述, 功能
3.3V 1:12 LVCMOS PLL Clock Generator
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016
MPC9772
DATA SHEET
The MPC9772 is a 3.3 V compatible, 1:12 PLL based clock generator targeted
for high performance low-skew clock distribution in mid-range to
high-performance networking, computing and telecom applications. With output
frequencies up to 240 MHz and output skews less than 250 ps the device meets
the needs of the most demanding clock applications.
Features
• 1:12 PLL Based Low-Voltage Clock Generator
• 3.3 V Power Supply
• Internal Power-On Reset
• Generates Cock Signals Up to 240 MHz
• Maximum Output Skew of 250 ps
• On-Chip Crystal Oscillator Clock Reference
• Two LVCMOS PLL Reference Clock Inputs
• External PLL Feedback Supports Zero-Delay Capability
• Various Feedback and Output Dividers (See Applications Information
Section)
• Supports Up to Three Individual Generated Output Clock Frequencies
• Synchronous Output Clock Stop Circuitry for Each Individual Output for
Power Down Support
• Drives Up to 24 Clock Lines
• Ambient Temperature Range 0C to +70C
• Pin and Function Compatible To the MPC972
• 52-Lead Pb-Free Package
For drop in replacement use 87972DYI-147
MPC9772
3.3 V 1:12 LVCMOS
PLL CLOCK GENERATOR
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 848D-03
Functional Description
The MPC9772 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC9772 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The
reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match
the VCO frequency range. The MPC9772 features an extensive level of frequency programmability between the 12 outputs as
well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1, and 8:3.
The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the
feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference
versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addi-
tion the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-
binary factor. The MPC9772 also supports the 180phase shift of one of its output banks with respect to the other output banks.
The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of sys-
tem baseline timing signals.
The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two
alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL
bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output
dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL char-
acteristics do not apply.
The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the
MPC9772. The MPC9772 has an internal power-on reset.
The MPC9772 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission
lines. For series terminated transmission lines, each of the MPC9772 outputs can drive one or two traces giving the devices an
effective fanout of 1:24. The device is pin and function compatible to the MPC972 and is packaged in a 52-lead LQFP package.
MPC9772 REVISION 8 3/16/16
1 ©2016 Integrated Device Technology, Inc.







MPC9772 pdf, 数据表
MPC9772 DATA SHEET
APPLICATIONS INFORMATION
MPC9772 Configurations
Configuring the MPC9772 amounts to properly configuring
the internal dividers to produce the desired output
frequencies. The output frequency can be represented by
this formula:
fOUT = fREF M N
fREF PLL VCO_SEL N fOUT
the specified frequency range. This divider is controlled by
the VCO_SEL pin. VCO_SEL effectively extends the usable
input frequency range while it has no effect on the output to
reference frequency ratio.
The output frequency for each bank can be derived from
the VCO frequency and output divider:
fQA[0:3] = fVCO (VCO_SEL NA)
fQB[0:3] = fVCO (VCO_SEL NB)
fQC[0:3] = fVCO (VCO_SEL NC)
M
where fREF is the reference frequency of the selected input
clock source (CCLKO, CCLK1 or XTAL interface), M is the
PLL feedback divider and N is a output divider. The PLL
feedback divider is configured by the FSEL_FB[2:0] and the
output dividers are individually configured for each output
bank by the FSEL_A[1:0], FSEL_B[1:0] and FSEL_C[1:0]
inputs.
The reference frequency fREF and the selection of the
feedback-divider M is limited by the specified VCO frequency
range. fREF and M must be configured to match the VCO
frequency range of 200 to 480 MHz in order to achieve stable
PLL operation:
fVCO,MIN (fREF VCO_SEL M) fVCO,MAX
The PLL post-divider VCO_SEL is either a divide-by-one
or a divide-by-two and can be used to situate the VCO into
Table 11. MPC9772 Divider
Divider
Function
VCO_SEL
Values
M PLL feedback
FSEL_FB[0:3]
1 4, 6, 8, 10, 12, 16
2 8, 12, 16, 20, 24, 32, 40
NA Bank A Output
Divider
FSEL_A[0:1]
1
2
4, 6, 8, 12
8, 12, 16, 24
NB Bank B Output
Divider
FSEL_B[0:1]
1
2
4, 6, 8, 10
8, 12, 16, 20
NC Bank C Output
Divider
FSEL_C[0:1]
1
2
2, 4, 6, 8
4, 8, 12, 16
Table 11 shows the various PLL feedback and output
dividers and Figure 3 and Figure 4 display example
configurations for the MPC9772:
REVISION 8 3/16/16
8 ©2016 Integrated Device Technology, Inc.







MPC9772 equivalent, schematic
MPC9772 DATA SHEET
Revision History Sheet
Rev Table Page Description of Change
7 1 NRND – Not Recommend for New Designs
8 Removed NRND and updated data sheet format
8
1 Product Discontinuation Notice - Last time buy expires September 7, 2016.
PDN N-16-02
Date
1/8/13
3/18/15
3/16/16
REVISION 8 3/16/16
16 ©2016 Integrated Device Technology, Inc.










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