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零件编号 | EV12AS200AZP | ||
描述 | ANALOG TO DIGITAL CONVERTER | ||
制造商 | e2v | ||
LOGO | |||
1 Page
EV12AS200AZP
ANALOG TO DIGITAL CONVERTER
12‐bit 1.5 GSps
Datasheet
Main features
• Single Core ADC Architecture with 12‐bit Resolution Integrating a Selectable 1:1 and 1:2 DEMUX
• 1.5 GSps Guaranteed Conversion Rate
• 500 mVpp Analog Input Voltage (Differential Full Scale and AC Coupled)
• Very Low Latency (< 5 Clock Cycles)
• Noise Floor of –150 dBm/Hz (13‐bit ENOB in 10 MHz Bandwidth)
• Analog and Clock Input Impedance: 100 Differential
• Power Dissipation: 3.0W (1:1 Mode) ; 3.1W (1:2 Mode)
• Differential Input Clock (AC Coupled)
• LVDS Differential Output Data and Data Ready on the 2 Output Ports
• Write only 3WSI‐like Digital Interface (Gain, Offset, Sampling Delay adjust, DMUX Ratio Selection, test Modes)
• ADC Gain, Offset, Sampling Delay Adjustment for Interleaving Control
• Dynamic Test Mode (Alignment Sequence)
• Power Supplies: VCCA5 = 5.0V, VCCA3 = 3.3V, VCCO = 2.5V or 3.3V
• Package: FpBGA196 15 x15 mm2 196 balls
Performances
• 2.3 GHz Full Power Input Bandwidth (–3 dB)
• Single Tone Performance:
SFDR = –66 dBFS; ENOB = 9.0‐Bit; SNR = 57 dBFS at Fin = 997 MHz @ –1 dBFS, Fs = 1.5 GSps
SFDR = –65 dBFS; ENOB = 8.8‐Bit; SNR = 56 dBFS at Fin = 1600 MHz @ –1 dBFS, Fs = 1.5 GSps
SFDR = –70 dBFS; ENOB = 9.3‐Bit; SNR = 59 dBFS at Fin = 997 MHz @ –12 dBFS, Fs = 1.5 GSps
SFDR = –70 dBFS; ENOB = 9.3‐Bit; SNR = 58.5 dBFS at Fin = 1600 MHz @ –12 dBFS, Fs = 1.5 GSps
• Broadband Performance:
NPR = 48 dB at –14 dBFS Optimum Loading Factor in 1st Nyquist
Applications
• Satellite Communications Systems
• Telecom Test Instrumentation
• Wireless Communications Systems
• Direct RF Down‐conversion
• Automatic Test Equipment
• Direct L‐Band RF Down Conversion
• Radar Systems
• High Resolution Oscilloscopes
e2v semiconductors SAS 2015
Visit our website: www.e2v.com
for the latest version of the datasheet
1122C–BDC–06/15
EV12AS200AZP
2.4 Dynamic Performance
Unless otherwise stated, values here below are typical values (typical conditions of operations) assuming an
external clock jitter of 75 fs rms (corresponds to e2v testbench value). ADC internal clock jitter is 75 fs rms.
Table 2‐4. Dynamic Performance
Parameter
Symbol
Min
Typ
AC Analog Inputs
Full power Input Bandwidth (Fclk = 1.5 GSps)
FPBW
2.3
Gain Flatness (from 10 to 170 MHz) (Fclk = 1.5 GSps)
Gain Flatness (from 170 to 1500 MHz) (Fclk = 1.5 GSps)
Gain Flatness (from 1500 to 1800 MHz) (Fclk = 1.5 GSps)
–1 dBFS differential input mode, 50% clock duty cycle, +4 dBm differential clock, external jitter = 75 fs rms max
Signal to Noise And Distortion Ratio
FS = 1 GSps Fin = 997 MHz
FS = 1.5 GSps Fin = 740 MHz
FS = 1.5 GSps Fin = 997 MHz
FS = 1.5 GSps Fin = 1600 MHz
SINAD
54.5
54.5
56
54.5
Effective Number of Bits
FS = 1 GSps Fin = 997 MHz
FS = 1.5 GSps Fin = 740 MHz
FS = 1.5 GSps Fin = 997 MHz
FS = 1.5 GSps Fin = 1600 MHz
ENOB
8.4
8.2
8.8
8.8
9.0
8.8
Signal to Noise Ratio
FS = 1 GSps Fin = 997 MHz
FS = 1.5 GSps Fin = 740 MHz
FS = 1.5 GSps Fin = 997 MHz
FS = 1.5 GSps Fin = 1600 MHz
57.0
SNR 56.5
55.5 57.0
54.5 56.0
Total Harmonic Distortion (25 harmonics)
FS = 1 GSps Fin = 997 MHz
FS = 1.5 GSps Fin = 740 MHz
FS = 1.5 GSps Fin = 997 MHz
FS = 1.5 GSps Fin = 1600 MHz
60
THD 60
61
60
Spurious Free Dynamic Range
FS = 1 GSps Fin = 997 MHz
FS = 1.5 GSps Fin = 740 MHz
FS = 1.5 GSps Fin = 997 MHz
FS = 1.5 GSps Fin = 1600 MHz
SFDR
54
53
62
63
66
65
Test
Max Unit Level
GHz
0.5 dB
1 dB
1.5 dB
dBFS
Bit FS
dBFS
dBFS
dBFS
1
4
1
1
1
4
1
1
1
4
1
1
1
4
1
1
1
4
1
1
8
1122C–BDC–06/15
e2v semiconductors SAS 2015
EV12AS200AZP
2.9 Definition of Terms
Table 2‐7.
Abbreviation
(Fs max)
(Fs min)
(BER)
(FPBW)
(SSBW)
(SINAD)
(SNR)
(THD)
(SFDR)
(ENOB)
(DNL)
(INL)
(TA)
(JITTER)
(TS)
(ORT)
(TOD)
(TDR)
(TPDR)
Definition of Terms
Term
Maximum Sampling
Frequency
Minimum Sampling
frequency
Bit Error Rate
Full power input
bandwidth
Small Signal Input
bandwidth
Signal to noise and
distortion ratio
Signal to noise ratio
Total harmonic
distortion
Spurious free dynamic
range
Effective Number Of Bits
Differential non linearity
Integral non linearity
Aperture delay
Aperture uncertainty
Settling time
Overvoltage recovery
time
Digital data Output
delay
Data ready output delay
Data ready pipeline
delay
Definition
Performances are warranted up to Fsmax unless specified.
Performances are warranted for sampling frequency above Fsmin.
Probability to exceed a specified error threshold for a sample at maximum specified sampling rate. An error
code is a code that differs by more than ±128 LSB from the correct code.
Analog input frequency at which the fundamental component in the digitally reconstructed output
waveform has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for input at
Full Scale –1 dB (– 1 dBFS).
Analog input frequency at which the fundamental component in the digitally reconstructed output
waveform has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for input at
Full Scale –10 dB (– 10 dBFS).
Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale (– 1 dBFS), to the RMS sum of
all other spectral components, including the harmonics except DC.
Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale, to the RMS sum of all other
spectral components excluding the twenty five first harmonics.
Ratio expressed in dB of the RMS sum of the first twenty five harmonic components, to the RMS input signal
amplitude, set at 1 dB below full scale. It may be reported in dB (i.e, related to converter –1 dB Full Scale), or
in dBc (i.e, related to input signal level).
Ratio expressed in dB of the RMS signal amplitude, set at 1 dB below Full Scale, to the RMS value of the
highest spectral component (peak spurious spectral component). The peak spurious component may or may
not be a harmonic. It may be reported in dB (i.e., related to converter
–1 dB Full Scale), or in dBc (i.e, related to input signal level).
ENOB = S‐‐‐‐I‐N‐‐‐‐A‐‐‐‐D‐‐‐‐ ‐‐‐‐‐ ‐1‐‐‐.‐‐7‐‐‐6‐‐‐‐ ‐+‐‐‐ ‐‐2‐‐‐0‐‐‐‐ ‐l‐‐o‐‐‐g‐‐‐ ‐‐(‐‐A‐‐‐ ‐‐/‐‐ ‐‐F‐‐‐S‐‐‐/‐‐2‐‐‐‐)
6.02
Where A is the actual input amplitude and FS is the full
scale range of the ADC under test
The Differential Non Linearity for an output code i is the difference between the measured step size of code
i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum value of all DNL (i). DNL error
specification of less than 1 LSB guarantees that there are no missing output codes and that the transfer
function is monotonic.
The Integral Non Linearity for an output code i is the difference between the measured input voltage at
which the transition occurs and the ideal value of this transition.
INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|.
Delay between the rising edge of the differential clock inputs (CLK, CLKN) (zero crossing point), and the time
at which (VIN,VINN) is sampled.
Sample to sample variation in aperture delay. The voltage error due to jitter depends on the slew rate of the
signal at the sampling point.
Time delay to achieve 0.2 % accuracy at the converter output when a 80% Full Scale step function is applied
to the differential analog input.
Time to recover 0.2 % accuracy at the output, after a 150 % full scale step applied on the input is reduced to
midscale.
Delay from the rising edge of the differential clock inputs (CLK, CLKN) (zero crossing point) to the next point
of change in the differential output data (zero crossing) with specified load.
Delay from the falling edge of the differential clock inputs (CLK, CLKN) (zero crossing point) to the next point
of change in the differential output data ready (zero crossing) with specified load.
Number of clock cycles between the sampling edge of an input data and the associated output data ready
being made available, (not taking in account the TDR).
16
1122C–BDC–06/15
e2v semiconductors SAS 2015
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页数 | 30 页 | ||
下载 | [ EV12AS200AZP.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
EV12AS200AZP | ANALOG TO DIGITAL CONVERTER | e2v |
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