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PDF ( 数据手册 , 数据表 ) 6551

零件编号 6551
描述 ASYNCHRONOUS COMMUNICATION INTERFACE ADAPTER
制造商 Commodore
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6551 数据手册, 描述, 功能
, . .commodore
~ aamiconduct:ar group
~~@~
MPS
6551
ASSYNCH RONOUS
COMMUNICATION
INTERFACE
ADAPTER
[ 6551 ASYNCHRONOUS COMMUNICATION INTERFACE ADAPTER
CONCEPT:
The 6551 is an Asynchronous Communication Adapter (ACIA) intended to provide for interfacing the 6500/6800
microprocessor families to serial communication data sets and modems. A unique feature is the inclusion of an
on-chip programmable baud rate generator, with a crystal being the only external com pone t required.
FEATURES:
• On-chip baud rate generator: 15 programmable baud
rates derived from a standard 1.8432 M Hz external
crystal (50 to 19,200 baud).
• Programmable interrupt and status register to simplify
software design.
• Single +5 volt power supply.
• Serial echo mode.
• False start bit detection.
• 8-bit bi-directional data bus for direct communicati~
)
-standard baud rates (up
engths; number of stop bits; and
nd detection.
control signals provided.
:¥ep';' none, mark, space).
r half-duplex operation.
9 bit transmission.
ORDER NUMBER
MXS 6551
PACKAGE DESIGNATOR
C = CERAMIC
P = PLASTIC
6551 PIN CONFIGURATION
GND 1
2
3
4
5
6
7
RTS 8
CTS 9
TxD 10
l5'i'R 11
RxD 12
RSO 13
RS1 14
28 R/W
27 ~2
26 iRa
25 DB7
24 DB6
23 DB5
22 DB4
21 DB3
20 DB2
19 DB1
18 DBO
17 DSR
16 DCD
15 Vce
2-129







6551 pdf, 数据表
I
MPS
6551
STATUS REGISTER
The Status Register is used to indicate to the processor
the status of various 6551 functions and is outlined in
Figure 8.
171elsH31211101
~
STATUS
Parity Error"
Framing Error·
Overrun-
Receive Data
Reginar Full
Transmit Data
Register Empty
~ DCD
~
IRQ
SET BY
No Error
1 = Error
0" No Error
1 ::a:: Error
0'" No Error
1 :II' Error
0= Not Full
1'0 Full
0= Not Empty
1 = Empty
0= DCD Low
1 = DCD H'gh
0= DSR Low
1 = DSR High
o = No Interrupt
1 = Interrupt
CLEARED BY
Salf Clearing""
Self Clearing··
Self Clearlng-"
R••d Receive
Oat. RegISter
Write Transmit
Data Reginer
Not Resellable
Reflects DCD
State
Not Resellable
Reflects 5SR
State
Read
Status Register
"NO INTERRUPT GENERATED FOR THESE CONDITIONS.
"CLEARED AUTOMATICALLY AFTER A READ OF RDR AND
THE NEXT ERROR FREE RECEIPT OF DATA
HARDWARE RESET
PROGRAM RESET
Figure 8. Status Register Format
TRANSMIT AND RECEIVE DATA: REGISTERS
These registers are used as temporary data storage for
the 6551 Transmit and Receive ci'rcuits. The Transmit
Data Register is characterized as follows:
a• Bit is the leading bit to be transmitted.
• Unused data bits are the high-order bits and are
"don't care" for transmission.
The Receive Data Register is characterized in a similar
fashion:
a• Bit is the leading bit received.
• Unused data bits are the high-order bits and are "0"
for the receiver.
• Parity bits are not contained in the Receive Data
Register, but are stripped-off after being used for
external parity checking. Parity and all unused high-
order bits are "0".
Figure 9 illustrates a single transmitted or received data
word, for the example of 8 data bits, parity, and 1 stop bit.
"MARK"
L 1011
I
START
BIT
DATA BITS
"MARK"
J7 I P 1_
IPAR1ITY
BIT
STOP BIT
Figure 9 Serial Data Stream Example
COMMODORE SEMICONDUCTOR GROUP reserves the right to make changes to any products herein to
improve reliability, function or design. COMMODORE SEMICONDUCTOR GROUP does not assume any
liability arising ot of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others.
2-136














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