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PDF ( 数据手册 , 数据表 ) 6532

零件编号 6532
描述 MEMORY / TIMER ARRAY
制造商 Commodore
LOGO Commodore LOGO 


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6532 数据手册, 描述, 功能
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~ aernlconduct:or group
[K!J~@~
MPS
6532
MEMORY,
I/O, TIMER
ARRAY
6532 (MEMORY, 110, TIMER ARRAY)
THE 8532 CONCEPT-
The 6532 Is designed to operate In conjunction with the MCS650X Microprocessor Family. It is
comprised of a 128 x 8 static RAM, two software controlled 8 bit bl-dlrectional data ports allowing
direct Interfacing between the microprocessor unit and peripheral devices, a software programmable
Interval timer with Interrupt capable of timing In various Intervals from 1 to 262,144 clock periods, and
a programmable edge detect circuit.
FEATURES OF THE 8532
• 8 bit bl-dlrectlonal Data Bus for direct
communication with the microprocessor
• Programmable edge-sensitive Interrupt
• 128 x 8 static RAM
• Two 8 bit bl-dlrectlonal data ports for
Interface to peripherals
• Two programmable 110 Peripheral Data
Direction Registers
• Programmable Interval Timer
• Programmable Interval Timer Interrupt
• TTL & CMOS compatible. peripheral lines
• Peripheral pins with Direct Transistor
Drive Capability
• High Impedance Three-State Data Pins
• 1MHz, 2MHz and 3MHz operation
ORDERING INFORMATION
MXS6532_~
FREQUENCY RANGE
NO SUFFIX = 1 MHz
A = 2 MHz
L...-_ _ _ _ _ _ PACKAGE DESIGNATOR
C=CERAMIC
P= PLASTIC
8532 PIN DESIGNATION
vss
.0.5
.0.4
"3
"2
AI
AD
PAD
p.o.,
PA2
PA3
PA4
PA5
PA6
PA7
P87
P86
P85
PB4
VOO
.0.6
02
CSI
CS2
liS
R/W
REs
OBO
DB,
DBz
OB3
DB4
085
086
OB7
I"RQ
PBO
P81
PBZ
PB3
2-107







6532 pdf, 数据表
MPS
6532
Interval nnw
The Timer section of the 6532 contains three basic parts: preliminary divide down register, programmable 8-blt
register and Interrupt logic.
Figure 2. BASIC ELEMENTS OF INTERVAL TIMER
RIW PA7 A3
I'
- INTERRUPT
CONTROL
D7 De D6 Dol D3 D2 D1 DO
I. r
RIW
PROGRAMMABLE
REGISTER
-
A1
rI
DIVIDE
DOWN
t2
07 De
.I ~ Ir
os EM 03 02 01 DO
The Interval time can be programmed to count up to 255 time intervals. Each time interval can be either 1T, 8T,
64T or 1024T Increments, where T is the system clock period. When a full count is reached, an interrupt flag is set
to a logic "1". After the Interrupt flag Is set the internal clock begins counting down to a maximum of - 255T. Thus,
after the Interrupt flag Is set, a Read of the timer wi" tell how long since the flag was set up to a maximum of 255T.
The 8 bit system Data Bus is used to transfer data to and from the Interval Timer. If a count of 52 time intervals
were to be counted, the pattern 0 0 1 1 0 1 0 0 would be put on the Data Bus and written into the Interval Time
register.
At the same time that data Is being written to the Interval Timer, the counting intervals of 1, 8, 64, 1024T are
decoded from address lines AO and A1. During a Read or Write operation address line A3 controls the interrupt
capability; I.e., A, = 1 enables IRO, A, = 0 disables IRO. When the timer is read prior to the interrupt flag being set,
the number of time Intervals remaining will be read, i.e., 51,50,49, etc.
When the timer has counted thru 00000000 on the next count time an interrupt will occur and the counter will
read 1 1 1 1 1 1 1 1. After Interrupt, the timer register decrements at a divide by "1" rate of the system clock. If after
Interrupt, the timer Is read and a value of 1 1 1 0 0 1 0 0 is read, the time since interrupt Is 27T. The value read is In
two's complement, but remember that interrupt occurred on count number. Therefore, we must subtract 1.
Value read = 1 1 1 0 0 1 0 0
Complement = 0 0 0 1 1 0 1 1
ADD 1
= 0 0 0 1 1 1 0 0 = 28 Equals two's complement of register
SUB 1
=00011011 =27
2-114














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