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PDF ( 数据手册 , 数据表 ) 6525

零件编号 6525
描述 TRI-PORT INTERFACE
制造商 Commodore
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6525 数据手册, 描述, 功能
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6525 TRI·PORT INTERFACE
MPS
6525
TRI-PORT
INTERFACE
CONCEPT ...
The 6525 TRI·PORT Interface (TPI) is designed to simplify the implementation of complex I/O
operations in microcomputer systems. It combines two dedicated a·bit 110 ports with a third a-bit port
programmable for either normal 110 operation or priority interrupt/handshaking control. Depending on
the mode selected, the 6525 can provide 24 individually programmable 110 lines or 16 110 lines, 2
handshake lines and 5 priority interrupt inputs.
FEATURES:
• 24 individually programmable 110 lines or
16 110 lines, 2 handshake lines and 5 in-
terrupt inputs.
• Priority or non-priority interrupts
• Automatic handshaking
• Completely static operation
• Two TTL Drive Capabi Iity
• a directly addressable registers
• 1 MHz, 2MHz and 3MHz operation
6525 REGISTERS
·000
001
010
011
100
101
110
111
RO PRA - Port Register A
R1 PRB - Port Register B
R2 PRC - Port Register C
R3 DDRA - Data Qirection Register A
R4 DDRB - Data Direction Register B
R5 DDRC - Data Qirection Register C
R6 CR-Control Register
R7 AIR-Active Interrupt Register
-NOTE: RS2. RS1, RSO respectively
ORDER NUMBER:
MXSM25
T
L SPEED RANGE
=NO SUFFIX 450 ns
A=225 ns
B = 155 ns
PACKAGE DESIGNATOR
C=CERAMIC
P=PLASTIC
2-76
6525 PIN CONFIGURATION
Vss
PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7
cs
R/W
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 DB7
39 DBB
38 DB5
37 DB4
36 DB3
35 DB2
34 DB1
33 DBO
32 PC7
31 PC6
30 PC5
29 PC4
26 PC3
27 PC2
26 PC1
25, pco
24 RSO
23 RS1
22' RS2
21 REs







6525 pdf, 数据表
MPS
6525
B. Lower priority interrupt received during active interrupt
1. 11 received and latched.
2. A1 is set and IRQ activated low.
3. Processor reads AIR to determine 11 is active.
4. AI R pushed onto stack and IL1 cleared.
5. AIR cleared and IRQ reset high.
6. Processor is servicing 11 while 10 occurs and sets
ILO·
7. Interrupt stack prevents lower priority ILO from
initiating a new interrupt.
8. Upon completion of 11 service, processor writes to
AIR, popping 11 interrupt out of stack.
9. ILO is now permitted to initiate a new interrupt
service.
C. Higher priority interrupt received during active interrupt
1. Interrupt 11 received and latched.
2. Al is set and IRQ activated low.
3. Processor reads AI R to determine 11 is active.
4. AI R is pushed onto stack and IL1 cleared.
5. AIR cleared and IRQ reset high.
6. Processor is servicing 11 when 12 occurs and sets
IL2· _
7. A2 is set and IRQ activated low because IL2 has
higher priority than 11 in stack.
8. Processor recognizes interrupt request and calls
interrupt service routine.
9. Processor reads AI R to determine 12 is active.
10. New AI R is pushed onto interrupt stack and IL2
cleared.
11. AI R cleared and IRQ reset high.
12. Processor services 12.
13. Upon completion of 12 service, processor writes to
AIR popping 12 interrupt from stack, restoring 11
status to top of stack (still preventing an 10 interrupt).
14. Processor return from interrupt resumes services of
suspended 11 routine.
15. Upon completion of 11, processor writes to AI R,
popping 11 interrupt from stack, leaving no active
interrupts.
6525 INTERFACE AND CONTROL
Initialization
A low on the RES pin clears all 6525 internal registers.
This puts the 6525 in Mode 0 with all three ports selected as
inputs (floating), preventing any conflicts on the bi-directional
port lines. For port pins to be used as outputs, the desired
output data may be written to the port register before
enabling the output driver. This sequence can eliminate
undesired output conditions when the outputs are enabled
via the DDR.
When selecting Mode 1, all interrupt inputs and IE3, IE4
must be stable before writing MC bit to "1." If this can not be
ensured, the interrupt latches (PRC4-PRCO) should be
cleared by writing 0 to PRC after MC=1 and before unmask-
ing the interrupt latches. Similarly, if CA and CB are to be
used as data transfer handshake lines, no PRA reads orPRB
writes should occur after RES or before actual data transfers
are to begin.
Processor Interface
The 6525 is a fully static device with interface charac-
teristics similar to a static RAM. To read, the RS and R/W
lines are stabilized and then CS is switched low, gating the
desired register onto the system data bus. (In 650X systems,
CS may be gated with .02). The system timing must accom-
modate both the TACC (address) and TCO (chip select)
delays before requiring valid data. To write to the 6525,
similar timing is required, with the processor providing valid
write data at least OS before CS switches high. To guarantee
proper operation of the 6525, THE R/W LINE MUST BE
STABLE ANY TIME CS IS LOW.
COMMODORE SEMICONDUCTOR GROUP reserves the right to make changes to any products herein to
improve reliability, function or design. COMMODORE SEMICONDUCTOR GROUP does not assume any
liability arising ot of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others.
2-83














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