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PDF ( 数据手册 , 数据表 ) 6501

零件编号 6501
描述 ONE-CHIP MICROCOMPUTER
制造商 Commodore
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6501 数据手册, 描述, 功能
, . .commodore
~ aarnlconduCl:ar group
~UYAJ@~
MPS
6500/1
ONE-CHIP
MICROCOMPUTER
8500/1 ONE-CHIP MICROCOMPUTER
INTRODucnoN
The MOS Technology 6500/1 Is a complete, high-performance 8-blt NMOS microcomputer on a single chip, and
Is totally upward/downward software compatible with all members of the 6500 family.
The 650011 consists of a 6502 CPU, an Internal clock oscillator, 2048 bytes of Read Only Memory (ROM), 64 bytes
of Random Access Memory (RAM) and flexible Interface circuitry. The· interface circuitry includes a 18-blt
programmable counter/latch with four operating modes, 32 bidirectional Input/output lines (Including two edge-
sensitive lines), five Interrupts and a counter I/O line.
PRODUCT SUPPORT
To allow prototype clrCl~lt development, Mos Tech-
nology offers a PROM compatible 64-pln Emulator de-
vice. This device provides all 650011 Interface lines
plus routing the address bus, data bus, and asso-
ciated control lines off the chip to be connected to
external memory.
Order
Number
ORDERING INFORMATION
Package Frequency Temperature
Type Option
Range
MPS65OOI1
Plastic 1 MHz
MCS6500/1 Ceramic 1 MHz
MPS65OOI1A Plastic 2 MHz
MCS65OOI1A Ceramic 2 MHz
MCS65OOI1E Emulator Device 1MHz
'MCS65OOI1EA Emulator Device 2MHz
O°C to 70°C
O°C to 70°C
O°C to 70°C
O°C to 70°C
Note: The RC frequency option is available only in the
1 MHz 6500/1.
XTU
)(flO
RES
Rgj
vee
vss
VRR
¢a;> PAO-PA7
¢a~ P8(H2B7
¢a ~ pc()'PC7
¢a::> POOPD7
CNTR
FEATURES
• 6502 CPU
-Software upward/downward compatibility
-Decimal or binary arithmetic modes
-13 addressing modes
-True direct and indirect indexing
-Memory addressable 110
• 2048 x 8 mask programmable ROM
• 64 x 8 static RAM
• 32 bi<iirectional TIL compatible 110 lines (4 ports)
• 1 bi<iirectional TIL compatible counter I/O line
• 16-bit programmable counter/latch with four
modes
-Interval Timer -Event Counter
-Pulse Generator -Pulse Width Measurement
• Five Interrupts
-Reset
-Non·maskable
-Two external edge sensitive
-Counter
• 1 of 3 frequency references
-Crystal -Clock -RC (resistor only)
• 4 MHz max crystal or clock external frequency
• 2 MHz or 1 MHz internal clock
• 1 /Ls minimum instruction execution
• N-channel, silicon gate, depletion load technology
• Single + 5V power supply
• 500 mW operating power
• Separate power pin for RAM
• 40 pin DIP
• 64 pin PROM compatible Emulator device
Interface Diagram
2-2







6501 pdf, 数据表
MPS
6500/1
INSTRUCTION SET
INSTRUCTION SET - OP CODES, Execution Time, Memory Requirements
AD C A . M' C - A 1.1111 119 2
AND
AS L
• CC
AI\M-A
1It:lt2
C... ~ ... I
.AAHeH ON C-I 121
I C 5 IA"HeH ON C·' 12/
I E Q IAANCH ON Z"
121
II T AI\M
I M I IRANCH ON N"
121
IN E IAANCH ON Z'I 121
I P L IAANCH ON N-I 121
• R II IS- F,. 11
I V C IRANCH ON V"
121
I \I S IRANCH ON V"
12/
CLC I-C
C L 0 1-0
C L 1 1-1
CLV I-V
x....CMP A-I\/I
C P II
11 CII 2
E. 2
CPY
oEC
o E II
V-M
M-l - M
II-I - I(
C' 2
DEY V-I-V
E 0 R A ... M - A
lit "II 2
INC M • 1 - M
IN II II "-11
INV Y"-V
J 101 P JUMP TO NEW LOC
J 5 A IS- F... 21 Jl.JMP SUI
LOA M-A
11 I A9 2
2 110. 3 IS J 2
220.321>32
'E II 3 II S 2 itA 2
2 CO.
2 EC.
2 CC.
CE II
3 CS 3
JU J
3 C. J
3 C6 S
2 "0" 3 .5 3 2
EE 6 3 E6 S 2
.C 3
21 6
2 AI).
J
J
3 A5 3
2
111 II
21 II
1
II 71
18 2
082
sa 2
18 2
1
1
1
1
CI II
CA 2
88 2
1
1
., 6
E8 2 1
ca 2 1
AI 6
2 11 S
2 31 S
2 01 S
2 SI S
2 II 5
2 1S. 2 10.
2 3S. 2 3D.
. III II 2 IE 1
2 OS. 2 00"
06 II 2 DE 7
2 5S. 2 SO"
Fa 6 2 FE 7
2 8S ". 2 BO.
3 19 •
3 311 •
3
3 09.
J
3 S9"
J
3 .9 "
II 2
.. 2
F, 2
]I 2
Dt 2
II 2
!it 2
7' 2
3
3
3
2
2
2
2
2
2
1--
6C 5
, f-"
3
- .:-=.
M, I -
- u.
...-
-
- -- --
--
-- I
,II
II I
J,
"I -
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IJ
.... , I ....' • . . . .
MU,," _ , I ....... '
LOll 101 - II
11 I A2 2 2 AE. 3 AI 3 2
IE" 3
II 4 2 " •
LOY M-Y
ClIA.2 2AC" 3A.3 2
L S R .....~ C U I 3 '" 5 2 "A 2 1
.... 28C. 3
5& I 2 IE 7 3
•• -
••"
N 0 P NO orEAATION
EA 2 1
ORA AVM-A
19 2 2.0. 3 H 3 2
" a 2 11 " 2 15" 2 10" 3 19. 3
PLA S'i-S
PLP 5"-5
ROL II.oIIIi
5-1-5
5-1-5
Ms-A
Ms-P
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2E II
3 26 5
2 2A 2
'" 3
.. 3
It.
:It.
1
1
I
1
I
.123£13
...IAESTOREDI
---
RORI~~~
.EI 3lts 26A2 1
111 II 2 7E 7 3
A T I IS-'.. 1l1lTRN INT.
"'II I
AESTOREDI
R T 5 IS- F.. 21 AT AN sua
I t II 1
SIC A......c-A
I1IE922EO"3E532
E1 a 2 F1 5 2 F5" 2 FD" 3 F9 " 3
• I 131 - - I
SEC l-C
31 2 1
~:;'::::'~+::"':::'~::"'-----+++-I~H+-++t-HI-+;=:f~~:t-+-1H-++++HHH-+++-IHH+++-1-H-t--_' --=----:-~-~--:
STA
STX
STY
TA II
TAY
TSII
T II A
TIIS
TVA
A-M
11-101
V-M
A-II
A-V
S-I(
II - A
II-S
V-A
10" 3 IS 3 2
8£" 3863 2
IC.3 ... 32
II • 2 91 a 2 9S" 2 90 5 3 99 5 3
M2
11.8 2
8A 2
811. 2
911. 2
911 2
1
1
1
1
~• 2
96. 2
111 ADD 1 TO .,.... IF PAGE BOUNDAAY IS CROSSED
121 ADt; 1 TO "N" IF IRANCH OCCURS TO SAME PAGE
ADD 2 TO "N" IF IRANCH OCCURS TO DIFFERENT PAGE
131 CAAAY NOT. IELOW
,.1 I.F IN DECIMAL MODE Z FLAG IS INVALID
ACCI,IIIIULATOR MUST If CHECKED FOR ZERO RESUl T
I( INDEX X
Y INDEx Y
A ACCUMULATOR
M MEMORY PER EfFECTIVE ADORESS
... MEMORV PER,STACK POINTER
• ADD
SUITRACT
II A"'D
\lOR
.., ("CLUSIVE OR
MODIFIED
..OT MODI' IE D
M MEMOR, 8,T 7
M MEMORY BIT 6
....0 CVCLES
NO BYTES
Note: MOS Technology cannot assume liability for the use of undefined OP Codes
2-9







6501 equivalent, schematic
COMMON CHARACTERISTICS
MPS
6500
Clock Tlmlng- 8S02, 03, 04, 05, 08, 07
r-+j TF00
l r-- TR00
~ ~/-1.5Y_______
I..14=-- PVYH00l
..
2.4Y
--\"...;:,.4.:.,Y_ __
PVYH00H-J
r- =\., _---J/l.SY
----l " - - -0.(O,UTl;.;..;.;_ _ _, I...-PVYH0,
-
Clock Tlmlng- 8512, 13, 14, 16
AIW
ADDRESS
FROM
MPU
DATA
FROM
MEMORY
S.O.
ROY
AIW
ADDRESS
FROM
MPU
DATA
FROM
MEMORY
5.0.
SYNC
I
Timing for Reading Data from Memory or Peripherals
I II
I
AIW
ADDRESS
FROM
MPU
DATA
FROM
MPU
2.0 Y' l_--+---<I...
0.8Y
TMOS
Timing for Writing Data to Memory or Peripherals
ROY
SYNC
I
Timing for Reading Data from Memory or Peripherals
I II
I
AIW
ADDRESS
FROM
MPU
DATA
FROM
MPU
2.0Y
O.8Y
TMOS
Timing for Writing Data to Memory or Peripheral.
2-17










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