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PDF ( 数据手册 , 数据表 ) MT9VDDF3272

零件编号 MT9VDDF3272
描述 256MB DDR SDRAM REGISTERED DIMM
制造商 Micron
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MT9VDDF3272 数据手册, 描述, 功能
DDR SDRAM
REGISTERED DIMM
256MB, 512MB (x72, ECC, SR)
184-PIN DDR SDRAM RDIMM
MT9VDDF3272 – 256MB
MT9VDDF6472 – 512MB
For the latest data sheet, please refer to the MicronWeb
site: www.micron.com/products/modules
Features
• 184-pin, dual, in-line memory module (DIMM)
• Fast data transfer rates: PC1600, PC2100, or PC2700
• Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR
SDRAM components
• Registered Inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• Supports ECC error detection and correction
• 256MB (32 Meg x 72); and 512MB (64 Meg x 72)
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/received
with data—i.e., source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 7.8125µs maximum average periodic refresh
interval
• Serial Presence-Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
OPTIONS
• Operating Temperature Range
Commercial (0°C TA +70°C)
Industrial (-40°C TA +85°C)
MARKING
none
I1
Table 1: Address Table
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
Figure 1: 184-Pin DIMM (MO-206)
Low-Profile 1.125in. (28.58mm) 256MB
Low-Profile 1.125in. (28.58mm) 512MB
Very Low-Profile 0.72in. (18.29mm)
OPTIONS
• Package
184-pin DIMM (standard)
184-pin DIMM (lead-free)1
• Memory Clock, Speed, CAS Latency2
6ns (167 MHz), 333 MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2.5
10ns (100 MHz), 200 MT/s, CL = 2
• PCB
Low-Profile 1.125in. (28.58mm)
Very Low-Profile 0.72in. (18.29mm)
MARKING
G
Y
-335
-2621
-26A1
-265
-202
NOTE: 1. Contact Micron for product availability.
2. CL = CAS (READ) Latency; Registered mode will
add one clock cycle to CL.
256MB
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (32 Meg x 8)
1K (A0–A9)
1 (S0#)
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (64 Meg x 8)
2K (A0–A9, A11)
1 (S0#)
pdf: 09005aef80e119b2, source: 09005aef807d56a1
DDF9C32_64x72G.fm - Rev. B 9/04 EN
1
©2004 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.







MT9VDDF3272 pdf, 数据表
256MB, 512MB (x72, ECC, SR)
184-PIN DDR SDRAM RDIMM
Figure 5: Functional Block Diagram – Very Low-Profile
S0#
BA0, BA1
A0-A12
RAS#
CAS#
CKE0
WE#
CK
CK#
RS0#
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
U6, U13
R
E
G
I
S
T
E
R
S
DM CS# DQS
DQ
DQ
DQ
DQ U1
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ U2
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ U3
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ U4
DQ
DQ
DQ
DQ
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS# DQS
DQ
DQ
DQ
DQ U8
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ U9
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ U10
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ U11
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ U5
DQ
DQ
DQ
DQ
CK0
CK0#
120
RS0#
RBA0, RBA1: DDR SDRAMs
RA0-RA12: DDR SDRAMs
RRAS#: DDR SDRAMs
RCAS#: DDR SDRAMs
RCKE0: DDR SDRAMs
RWE#: DDR SDRAMs
RESET
SCL
WP
VDDSPD
VDDQ
VDD
VREF
VSS
U12
PLL
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
REGISTER X 2
U7
SERIAL PD
A0 A1 A2
SA0 SA1 SA2
SDA
SPD/EEPROM
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs, EEPROM
NOTE:
1. Unless otherwise noted, resistor values are 22.
2. Per industry standard, Micron utilizes various component speed grades as
referenced in the Module Part Numbering Guide at www.micron.com/num-
berguide.
Standard modules use the following DDR SDRAM devices:
MT46V32M8FG (256MB); MT46V64M8FG (512MB)
Lead-free modules use the following DDR SDRAM devices:
MT46V32M8BG (256MB); MT46V64M8BG (512MB)
pdf: 09005aef80e119b2, source: 09005aef807d56a1
DDF9C32_64x72G.fm - Rev. B 9/04 EN
8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.







MT9VDDF3272 equivalent, schematic
256MB, 512MB (x72, ECC, SR)
184-PIN DDR SDRAM RDIMM
Table 13: IDD Specifications and Conditions – 512MB
DDR SDRAM components only
Notes: 1–5, 8, 10, 12, 48; notes appear on pages 20–23; 0°C TA +70°C; VDD = VDDQ = +2.5V ±0.2V
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge;
tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs
changing once per clock cyle; Address and control inputs
changing once every two clock cycles
OPERATING CURRENT: One device bank; Active -Read Precharge;
Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN);
IOUT = 0mA; Address and control inputs changing once per clock
cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK =
tCK MIN; CKE = HIGH; Address and other control inputs changing
once per clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode; tCK = tCK (MIN);
CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge; tRC = tRAS (MAX);
tCK = tCK (MIN); DQ, DM andDQS inputs changing twice per
clock cycle; Address and other control inputs changing once per
clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once
per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle
AUTO REFRESH CURRENT
tREFC = tRFC (MIN)
tREFC = 7.8125µs
SELF REFRESH CURRENT: CKE 0.2V
OPERATING CURRENT: Four device bank interleaving READs (BL =
4) with auto precharge, tRC = tRC (MIN);
tCK = tCK (MIN); Address and control inputs change only during
Active READ, or WRITE commands
SYM
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD5A
IDD6
IDD7
-335
1,170
1,440
45
405
315
450
1,485
1,575
2,610
90
45
3,645
MAX
-262
1,170
1,440
45
405
315
450
1,485
1,395
2,610
90
45
3,600
-26A/
-265/
-202
1,035
UNITS NOTES
mA 20, 42
1,305 mA 20, 42
45 mA 21, 28,
44
360 mA
45
270 mA 21, 28,
44
405 mA
41
1,305 mA 20, 42
1,215 mA
20
2,520 mA 20, 44
90 mA 24, 44
45 mA
9
3,150 mA 20, 43
pdf: 09005aef80e119b2, source: 09005aef807d56a1
DDF9C32_64x72G.fm - Rev. B 9/04 EN
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.










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