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PDF ( 数据手册 , 数据表 ) MT9HTF12872AY

零件编号 MT9HTF12872AY
描述 1GB DDR2 SDRAM UDIMM
制造商 Micron
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MT9HTF12872AY 数据手册, 描述, 功能
256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM
Features
DDR2 SDRAM UDIMM
MT9HTF3272AY – 256MB
MT9HTF6472AY – 512MB
MT9HTF12872AY – 1GB
Features
240-pin, unbuffered dual in-line memory module
Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
256MB (32 Meg x 72), 512MB (64 Meg x 72), or 1GB
(128 Meg x 72)
VDD = VDDQ 1.8V
VDDSPD = 1.7–3.6V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
Single rank
Multiple internal device banks for concurrent
operation
Programmable CAS latency (CL)
Posted CAS# additive latency (AL)
WRITE latency = READ latency - 1 tCK
Programmable burst lengths (BL): 4 or 8
Adjustable data-output drive strength
64ms, 8192-cycle refresh
On-die termination (ODT)
Serial presence detect (SPD) with EEPROM
Gold edge contacts
Figure 1: 240-Pin UDIMM (MO-237 R/C A/F)
Module height 30.0mm (1.18in)
Options
Operating temperature
Commercial (0°C TA +70°C)
Industrial (–40°C TA +85°C)1
Package
240-pin DIMM (lead-free)
Frequency/CL2
2.5ns @ CL = 5 (DDR2-800)3, 4
2.5ns @ CL = 6(DDR2-800)3, 4
3.0ns @ CL = 6 (DDR2-667)
3.75ns @ CL = 5 (DDR2-53E)
5.0ns @ CL = 5 (DDR2-40E)
Marking
None
I
Y
-80E
-800
-667
-53E
-40E
Notes:
1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency.
3. Contact Micron for product availability.
4. Not available in 256MB density.
Table 1: Key Timing Parameters
Speed
Grade
-80E
-800
-667
-53E
-40E
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
CL = 6
800
800
Data Rate (MT/s)
CL = 5
CL = 4
800 533
667 533
667 553
553
400
CL = 3
400
400
400
400
400
tRCD
(ns)
12.5
15
15
15
15
tRP
(ns)
12.5
15
15
15
15
tRC
(ns)
55
55
55
55
55
PDF: 09005aef80e8ad4d
htf9c32_64_128x72ay – Rev. F 3/10 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.







MT9HTF12872AY pdf, 数据表
256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR2
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 8: Pin Descriptions
Symbol
Ax
Type
Input
BAx
CKx,
CK#x
CKEx
DMx,
Input
Input
Input
Input
ODTx
Input
Par_In
RAS#, CAS#, WE#
RESET#
S#x
SAx
SCL
CBx
DQx
DQSx,
DQS#x
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, and MR3) is loaded during the LOAD MODE command.
Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DDR2 SDRAM.
Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs: Used to configure the SPD EEPROM address range on the I2C
bus.
Serial clock for SPD EEPROM: Used to synchronize communication to and from the
SPD EEPROM on the I2C bus.
Check bits. Used for system error detection and correction.
Data input/output: Bidirectional data bus.
Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the con-
troller. Output with read data; input with write data for source synchronous opera-
tion. DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command.
PDF: 09005aef80e8ad4d
htf9c32_64_128x72ay – Rev. F 3/10 EN
8 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.







MT9HTF12872AY equivalent, schematic
256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM
IDD Specifications
Table 13: DDR2 IDD Specifications and Conditions (Die Revision A) – 1GB
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
Parameter
-80E/
Symbol -800 -667 -53E -40E Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC =
tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
IDD0
900 810 720 630 mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL =
4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
(IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data pattern is same as IDD4W
Precharge power-down current: All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
IDD1
IDD2P
990 900 855 720 mA
63 63 63 63 mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); IDD2Q 585 495 369 315 mA
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is IDD2N 630 540 405 360 mA
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
Active power-down current: All device banks open; tCK
= tCK (IDD); CKE is LOW; Other control and address bus in-
puts are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
IDD3P
405 360 315 315 mA
126 126 126 126
Active standby current: All device banks open; tCK = tCK (IDD), tRAS =
IDD3N 675 630 495 405 mA
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
IDD4W
IDD4R
IDD5
1665 1440 1170 990
1710 1440 1305 990
2520 2700 2250 1980
mA
mA
mA
Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
IDD6 63 63 63 63 mA
PDF: 09005aef80e8ad4d
htf9c32_64_128x72ay – Rev. F 3/10 EN
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.










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