DataSheet8.cn


PDF ( 数据手册 , 数据表 ) MT8HTF12864AY

零件编号 MT8HTF12864AY
描述 1GB DDR2 SDRAM UDIMM
制造商 Micron
LOGO Micron LOGO 


1 Page

No Preview Available !

MT8HTF12864AY 数据手册, 描述, 功能
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features
DDR2 SDRAM UDIMM
MT8HTF3264AY – 256MB
MT8HTF6464AY – 512MB
MT8HTF12864AY – 1GB
Features
240-pin, unbuffered dual in-line memory module
Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, PC2-6400, or PC2-8500
256MB (32 Meg x 64), 512MB (64 Meg x 64),
or 1GB (128 Meg x 64
VDD = VDDQ = 1.8V
VDDSPD = 1.7–3.6V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
Multiple internal device banks for concurrent
operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1 tCK
Programmable burst lengths (BL): 4 or 8
Adjustable data-output drive strength
64ms, 8192-cycle refresh
On-die termination (ODT)
Serial presence detect (SPD) with EEPROM
Gold edge contacts
Single rank
Figure 1: 240-Pin UDIMM (MO-237 R/C A and D)
PCB height: 30.0mm (1.18in)
Options
Operating temperature
Commercial (0°C TA +70°C)
Industrial (–40°C TA +85°C)1
Package
240-pin DIMM (lead-free)
Frequency/CL2
1.875ns @ CL = 7 (DDR2-1066)3
2.5ns @ CL = 5 (DDR2-800)
2.5ns @ CL = 6 (DDR2-800)
3.0ns @ CL = 5 (DDR2-667)
3.75ns @ CL = 4 (DDR2-533)4
5.0ns @ CL = 3 (DDR2-400)
Marking
None
I
Y
-1GA
-80E
-800
-667
-53E
-40E
Notes:
1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency.
3. Available only in 1GB, Rev. E devices.
4. Not recommended for new designs.
Table 1: Key Timing Parameters
Speed
Grade
-1GA
-80E
-800
-667
-53E
-40E
Industry
Nomenclature
PC2-8500
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
CL = 7
1066
Data Rate (MT/s)
CL = 6 CL = 5 CL = 4
800 667 533
800 800 533
800 667 533
667 553
– – 553
– – 400
CL = 3
400
400
400
400
400
400
tRCD
(ns)
13.125
12.5
15
15
15
15
tRP
(ns)
13.125
12.5
15
15
15
15
tRC
(ns)
58.125
57.5
60
60
55
55
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.







MT8HTF12864AY pdf, 数据表
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Functional Block Diagram
Figure 3: Functional Block Diagram – Alternate Clock
S0#
VSS
DQS0#
DQS0
DM0
DQS1#
DQS1
DM1
DQS2#
DQS2
DM2
DQS3#
DQS3
DM3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
U1
DQ
DQ
DQ
DQ
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
U2
DQ
DQ
DQ
DQ
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
U3
DQ
DQ
DQ
DQ
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
U4
DQ
DQ
DQ
DQ
DQS4#
DQS4
DM4
DQS5#
DQS5
DM5
DQS6#
DQS6
DM6
DQS7#
DQS7
DM7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
U5
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
U6
BA[2/1:0]
A[13:0]
RAS#
CAS#
WE#
CKE0
ODT0
VSS
VSS
VDDSPD
VDD/VDDQ
VREF
VSS
BA[2/1:0]: DDR2 SDRAM
A[13:0]: DDR2 SDRAM
RAS#: DDR2 SDRAM
CAS#: DDR2 SDRAM
WE#: DDR2 SDRAM
CKE0: DDR2 SDRAM
ODT0: DDR2 SDRAM
SPD EEPROM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
U7
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
U8
U9
SCL SPD EEPROM
WP A0 A1 A2
SDA
VSS SA0 SA1 SA2
CK0
CK0#
CK1
CK1#
CK2
CK2#
U1–U4
U5–U8
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
8 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.







MT8HTF12864AY equivalent, schematic
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
Table 12: DDR2 IDD Specifications and Conditions – 1GB
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
Parameter
Symbol -667 -53E -40E Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC
IDD0 720 640 560 mA
(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL
= CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD =
tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
puts are switching; Data pattern is same as IDD4W
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are float-
ing
IDD1
IDD2P
800 760 640 mA
56 56 56 mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
IDD2Q
440 328 280 mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD2N
480 360 320 mA
Active power-down current: All device banks open; tCK = Fast PDN exit IDD3PF 320 240 200 mA
tCK (IDD); CKE is LOW; Other control and address bus inputs are MR[12] = 0
stable; Data bus inputs are floating
Slow PDN exit IDD3PS 80 80 80
MR[12] = 1
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are switching
IDD3N
560 440 360 mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP =
tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are switching; Data bus inputs are switching
IDD4W
1280 1040 880
mA
Operating burst read current: All device banks open; Continuous burst read,
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
IDD4R
IDD5
IDD6
1280 1160 880 mA
2080 2000 1760 mA
56 56 56 mA
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK
(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is
HIGH between valid commands; Address bus inputs are stable during deselects;
Data bus inputs are switching
IDD7
2400 2320 2080 mA
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.










页数 18 页
下载[ MT8HTF12864AY.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
MT8HTF12864AY1GB DDR2 SDRAM UDIMMMicron
Micron

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap