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PDF ( 数据手册 , 数据表 ) MT4LSDT464H

零件编号 MT4LSDT464H
描述 32MB SMALL-OUTLINE SDRAM MODULE
制造商 Micron
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MT4LSDT464H 数据手册, 描述, 功能
SMALL-OUTLINE
SDRAM MODULE
Features
• PC100 and PC133 compliant 144-pin, small-outline,
dual in-line memory module (SODIMM)
• Utilizes 125 MHz and 133 MHz SDRAM
components
• Unbuffered
• 32MB (4Meg x 64), 64MB (8 Meg x 64), and 128MB
(16 Meg x 64)
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode: Standard and Low Power
• 32MB and 64MB: 64ms, 4,096-cycle refresh
(15.625µs refresh interval); 128MB: 64ms, 8,192-
cycle refresh (7.81µs refresh interval)
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)
• Gold edge contacts
Table 1: Timing Parameters
CL = CAS (READ) latency
ACCESS TIME
MODULE CLOCK
SETUP HOLD
MARKING FREQUENCY CL = 2 CL = 3 TIME TIME
-13E
-133
-10E
133 MHz
133 MHz
100 MHz
5.4ns
6ns2
5.4ns
1.5ns
1.5ns
2ns
0.8ns
0.8ns
1ns
32MB, 64MB, 128MB (x64, SR)
144-PIN SDRAM SODIMM
MT4LSDT464(L)H(I) – 32MB
MT4LSDT864(L)H(I) – 64MB
MT4LSDT1664(L)H(I) – 128MB
For the latest data sheet, please refer to the Micron® Web
site: www.micron.com/products/modules
Figure 1: 144-Pin SODIMM (MO-190)
Standard 1.00in. (25.40 mm)
Options
Marking
• Self Refresh Current
Standard
Low-Power
None
L1, 2
• Operating Temperature Range
Commercial (0°C to + 65°C)
Industrial (-40°C to +85°C)
None
I1, 2
• Package
144-pin SODIMM (standard)
144-pin SODIMM (lead-free)
G
Y1
• Memory Clock/CAS Latency
7.5ns (133 MHz)/CL = 2
-13E
7.5ns (133 MHz)/CL = 3
-133
10ns (100 MHz)/CL = 2
-10E
NOTE: 1. Contact Micron for product availability.
2. Low Power and Industrial Temperature options
not available concurrently; Industrial Tempera-
ture option available in -133 speed only.
Table 2: Address Table
Refresh Count
Device Banks
Device Configuration
Row Addressing
Column Addressing
Module Ranks
32MB
4K
4 (BA0, BA1)
64Mb (4 Meg x16)
4K (A0–A11)
256 (A0–A7)
1 (S0#)
64MB
4K
4 (BA0, BA1)
128Mb (8 Meg x 16)
4K (A0–A11)
512 (A0–A8)
1 (S0#)
128MB
8K
4 (BA0, BA1)
256Mb (16 Meg x 16)
8K (A0–A12)
512 (A0–A8)
1 (S0#)
09005aef80748a77
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
1 ©2004 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.







MT4LSDT464H pdf, 数据表
Mode register bits M0–M2 specify the burst length,
M3 specifies the type of burst (sequential or inter-
leaved), M4–M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
burst mode, and M10 and M11 are reserved for future
use. For 32MB and 64MB, M12 (A12) is undefined, but
should be driven LOW during loading of the mode reg-
ister.
The mode register must be loaded when all device
banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.
Burst Length
Read and write accesses to the SDRAM are burst ori-
ented, with the burst length being programmable, as
shown in Figure 4, Mode Register Definition Diagram.
The burst length determines the maximum number of
column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 1, 2, 4, or
8 locations are available for both the sequential and
the interleaved burst types, and a full-page burst is
available for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE
command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached, as shown in the Table 6,
Burst Definition Table, on page 9. The block is
uniquely selected by A1–Ai (where i is the most signifi-
cant column address bit for a given device configura-
tion) when the burst length is set to two; by A2–Ai
when the burst length is set to four; and by A3–Ai when
the burst length is set to eight. See Note 8 of Table 6,
Burst Definition Table, on page 9 for Ai values. The
remaining (least significant) address bit(s) is (are) used
to select the starting location within the block. Full-
page bursts wrap within the page if the boundary is
reached, as shown in Table 6, Burst Definition Table,
on page 9.
32MB, 64MB, 128MB (x64, SR)
144-PIN SDRAM SODIMM
Figure 4: Mode Register Definition
Diagram
32MB and 64MB Module
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
11 10 9 8 7
Reserved* WB Op Mode
6 543
CAS Latency BT
2 10
Burst Length
*Should program
M11, M10 = “0, 0”
to ensure compatibility
with future devices.
Mode Register (Mx)
128MB Module
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
12 11 10 9 8 7
Reserved* Reserved* WB Op Mode
6 54 3
CAS Latency BT
2 10
Burst Length
Mode Register (Mx)
*Should program
M12, M11, M10 = “0, 0, 0”
to ensure compatibility
with future devices.
M2 M1 M0
000
001
010
011
100
101
110
111
Burst Length
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 Burst Type
0 Sequential
1 Interleaved
M6 M5 M4
00 0
01 0
01 1
10 0
10 1
11 0
11 1
CAS Latency
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M8 M7 M6-M0 Operating Mode
0 0 Defined Standard Operation
--
- All other states reserved
M9 Write Burst Mode
0 Programmed Burst Length
1 Single Location Access
09005aef80748a77
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.







MT4LSDT464H equivalent, schematic
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD, VDDQ = +3.3V;
f = 1 MHz; TA = 25°C; pin under test biased at
1.4V.
3. IDD is dependent on output loading and cycle
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation
over the full temperature range is ensured (Com-
mercial temperature: 0°C TA +70°C and Indus-
trial Temperature: -40°C TA +85°C).
6. An initial pause of 100µs is required after power-
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (VDD
and VDDQ must be powered up simultaneously.
VSS and VSSQ must be at the same potential.) The
two AUTO REFRESH command wake-ups should
be repeated any time the tREF refresh require-
ment is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specifi-
cation, the clock and CKE must transit between
VIH and VIL (or between VIL and VIH) in a mono-
tonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
10. tHZ defines the time at which the output achieves
the open circuit condition; it is not a reference to
VOH or VOL. The last valid data element will meet
tOH before going High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V,
with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1ns, then
the timing is referenced at VIL (MAX) and VIH (MIN)
and no longer at the 1.5V crossover point.
12. Other input signals are allowed to transition no
more than once every two clocks and are other-
wise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is
properly initialized.
14. Timing actually specified by tCKS; clock(s) speci-
fied as a reference only at minimum cycle rate.
32MB, 64MB, 128MB (x64, SR)
144-PIN SDRAM SODIMM
15. Timing actually specified by tWR plus tRP; clock(s)
specified as a reference only at minimum cycle
rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC function-
ality and are not dependent on any timing param-
eter.
18. The IDD current will increase or decrease propor-
tionally according to the amount of frequency
alteration for the test condition.
19. Address transitions average one transition every
two clocks.
20. CLK must be toggled a minimum of two times
during this period.
21. Based on tCK = 10ns for -10E, and tCK = 7.5ns for
-133 and -13E.
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse
width 3ns, and the pulse width cannot be
greater than one third of the cycle rate. VIL under-
shoot: VIL (MIN) = -2V for a pulse width 3ns.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing tWR, and PRECHARGE commands). CKE may
be used to reduce the data rate.
24. Auto precharge mode only. The precharge timing
budget (tRP) begins 7ns for -13E; 7.5ns for -133
and 7ns for -10E after the first clock delay, after
the last WRITE is executed. May not exceed limit
set for precharge mode.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27. tAC for -133/-13E at CL = 3 with no load is 4.6ns
and is guaranteed by design.
28. Parameter guaranteed by design.
29. For -10E, CL= 2 and tCK = 10ns; for -133, CL = 3
and tCK = 7.5ns; for -13E, CL = 2 and tCK = 7.5ns.
30. CKE is HIGH during refresh command period
tRFC (MIN) else CKE is LOW. The IDD6 limit is
actually a nominal value and does not result in a
fail value.
31. The value of tRAS used in -13E speed grade mod-
ule SPDs is calculated from tRC - tRP = 45ns.
32. Refer to device data sheet for timing waveforms.
33. Leakage number reflects the worst case leakage
possible through the module pin, not what each
memory device contributes.
09005aef80748a77
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.










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