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PDF ( 数据手册 , 数据表 ) MT4LSDT1664A

零件编号 MT4LSDT1664A
描述 128MB SDRAM Unbuffered DIMM
制造商 Micron
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MT4LSDT1664A 数据手册, 描述, 功能
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Features
SDRAM Unbuffered DIMM (UDIMM)
MT4LSDT464A – 32MB
MT4LSDT864A(I) – 64MB
MT4LSDT1664A(I) – 128MB
For component data sheets, refer to Micron’s Web site: www.micron.com
Features
• 168-pin, dual in-line memory module (DIMM)
• PC100- and PC133-compliant
• Unbuffered
• 32MB (4 Meg x 64)2, 64MB (8 Meg x 64),
128MB (16 Meg x 64)
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes CONCURRENT AUTO
PRECHARGE and auto refresh modes
• Self refresh mode: 64ms, 4,096-cycle refresh
for 32MB and 64MB; 64ms, 8,192-cycle refresh
for 128MB
• LVTTL-compatible inputs and outputs
• Serial presence-detect (SPD)
• Gold edge contacts
Figure 1: 168-Pin DIMM (MO-161)
Standard 25.4mm (1.0in)
Options
• Package
– 168-pin DIMM (standard)
– 168-pin DIMM (Pb-free)
• Operating temperature range
– Commercial (0°C to +65°C)
– Industrial (–40°C to +85°C)1, 3
• Frequency/CAS Latency
– 7.5ns (133 MHz)/CL = 2
– 7.5ns (133 MHz)/CL = 3
– 8ns (100 MHz)/CL = 22
• PCB
– Standard 25.40mm (1.0in)
Marking
G
Y
None
I
-13E
-133
-10E
Notes: 1. Contact Micron for product availability.
2. Not recommended for new designs.
3. Industrial temperature option available in
-133 MHz only.
Table 1:
Key Timing Parameters
CL = CAS (READ) latency
Speed Grade
-13E
-133
-10E2
Industry
Nomenclature
PC133
PC133
PC100
Access Time
CL = 2
5.4ns
9ns
CL = 3
5.4ns
7.5ns
Setup Time
-13E
-133
-10E
Hold Time
133 MHz
133 MHz
100 MHz
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.







MT4LSDT1664A pdf, 数据表
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Mode Register Definition
defined as a signal cycling within timing constraints specified for the clock pin), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands should be
applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All device
banks must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO
REFRESH cycles are complete, the SDRAM is ready for mode register programming.
Because the mode register will power up in an unknown state, it should be loaded prior
to applying any operational command.
Mode Register Definition
The mode register is used to define the specific mode of operation of the SDRAM. This
definition includes the selection of a burst length, a burst type, a CAS latency, an oper-
ating mode, and a write burst mode, as shown in Figure 4 on page 10. The mode register
is programmed via the LOAD MODE REGISTER command and will retain the stored
information until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst
(sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the oper-
ating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future
use. For the 128MB module, address A12 (M12) is undefined but should be driven LOW
during loading of the mode register.
The mode register must be loaded when all device banks are idle, and the controller
must wait the specified time before initiating the subsequent operation. Violating either
of these requirements will result in unspecified operation.
Burst Length (BL)
Read and write accesses to the SDRAM are burst oriented, with the burst length being
programmable, as shown in Figure 4 on page 10. The burst length determines the
maximum number of column locations that can be accessed for a given READ or WRITE
command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and
the interleaved burst types, and a full-page burst is available for the sequential type. The
full-page burst is used in conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached, as shown in
Table 6 on page 11. The block is uniquely selected by A1–Ai when BL = 2, A2–Ai when BL
= 4, and A3–Ai when BL = 8. See note 8 of Table 6 on page 11 for Ai values. The remaining
(least significant) address bit(s) is (are) used to select the starting location within the
block. Full-page bursts wrap within the page if the boundary is reached, as shown in
Table 6 on page 11.
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.







MT4LSDT1664A equivalent, schematic
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Electrical Specifications
Table 11: AC Functional Characteristics (Continued)
Notes: 5, 6, 8, 9, 11, 31; notes appear on page 20
Parameter
Data-out to high-impedance from PRECHARGE
command
CL = 3
CL = 2
Symbol
tROH(3)
tROH(2)
-13E
3
2
-133
3
2
-10E
3
2
Units
tCK
tCK
Notes
17
17
Table 12: Electrical Characteristics and Recommended AC Operating Conditions
Notes: 5, 6, 8, 9, 11, 31; notes appear on page 20; VDD, VDDQ = +3.3V ±0.3V
AC Characteristics
-13E
-133
-10E
Parameter
Symbol
Access time from CLK
(positive edge)
CL = 3
CL = 2
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
CL = 3
CL = 2
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time CL = 3
CL = 2
Data-out low-impedance time
Data-out hold time (load)
Data-out hold time (no load)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (8,192 rows)
AUTO REFRESH period
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b
command
Transition time
WRITE recovery time
tAC(3)
tAC(2)
tAH
tAS
tCH
tCL
tCK(3)
tCK(2)
tCKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ(3)
tHZ(2)
tLZ
tOH
tOHN
tRAS
tRC
tRCD
tREF
tRFC
tRP
tRRD
tT
tWR
Exit SELF REFRESH to ACTIVE command tXSR
Min
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
0.8
1.5
0.8
1.5
1
3
1.8
37
60
15
66
15
14
0.3
1 CLK +
7ns
14
67
Max
5.4
5.4
5.4
5.4
120,000
64
1.2
Min
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
0.8
1.5
0.8
1.5
1
3
1.8
44
66
20
66
20
15
0.3
1 CLK +
7.5ns
15
75
Max
5.4
6
5.4
6
120,000
64
Min
1
2
3
3
8
10
1
2
1
2
1
2
1
3
1.8
50
70
20
70
20
20
Max Units
6
6
6
120,000
64
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
1.2 0.3 1.2
– 1 CLK + –
7ns
– 15 –
– 80 –
ns
ns
ns
ns
Notes
27
23
23
10
10
28
32
7
24
25
20
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.










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