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PDF ( 数据手册 , 数据表 ) MT4HTF6464AY

零件编号 MT4HTF6464AY
描述 512MB DDR2 SDRAM UDIMM
制造商 Micron
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MT4HTF6464AY 数据手册, 描述, 功能
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features
DDR2 SDRAM UDIMM
MT4HTF1664AY – 128MB
MT4HTF3264AY – 256MB
MT4HTF6464AY – 512MB
Features
240-pin, unbuffered dual in-line memory module
(UDIMM)
Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
128MB (16 Meg x 64), 256MB (32 Meg x 64),
512MB (64 Meg x 64)
VDD = VDDQ = 1.8V
VDDSPD = 1.7–3.6V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
Multiple internal device banks for concurrent
operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1 tCK
Programmable burst lengths (BL): 4 or 8
Adjustable data-output drive strength
64ms, 8192-cycle refresh
On-die termination (ODT)
Serial presence detect (SPD) with EEPROM
Gold edge contacts
Single rank
Figure 1: 240-Pin UDIMM (MO-237 R/C C)
Module height 30.0mm (1.18in)
Options
Operating temperature
Commercial (0°C TA +70°C)
Industrial (–40°C TA +85°C)1
Package
240-pin DIMM (lead-free)
Frequency/CL2
2.5ns @ CL = 5 (DDR2-800)4
2.5ns @ CL = 6 (DDR2-800)4
3.0ns @ CL = 5 (DDR2-667)
3.75ns @ CL = 4 (DDR2-533)3
5.0ns @ CL = 3 (DDR2-400)3
Marking
None
I
Y
-80E
-800
-667
-53E
-40E
Notes:
1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency.
3. Contact Micron for product availability.
4. Not available in 128MB and 256MB.
Table 1: Key Timing Parameters
Speed
Grade
-80E
-800
-667
-53E
-40E
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
CL = 6
800
800
Data Rate (MT/s)
CL = 5
CL = 4
800 533
667 533
667 553
553
400
CL = 3
400
400
400
400
400
tRCD
(ns)
12.5
15
15
15
15
tRP
(ns)
12.5
15
15
15
15
tRC
(ns)
55
55
55
55
55
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.







MT4HTF6464AY pdf, 数据表
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in the device data sheet are not implied. Exposure to
absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 8: Absolute Maximum Ratings
Symbol
VDD/VDDQ
VIN, VOUT
II
IOZ
IVREF
TA
TC1
Parameter
VDD/VDDQ supply voltage relative to VSS
Voltage on any pin relative to VSS
Input leakage current; Any input 0V VIN VDD; Address inputs, RAS#,
VREF input 0V VIN 0.95V; (All other pins not CAS#, WE#, S#, CKE,
under test = 0V)
ODT, BA
CK, CK#
DM
Output leakage current; 0V VOUT VDDQ; DQ DQ, DQS, DQS#
and ODT are disabled
VREF leakage current; VREF = valid VREF level
Module ambient operating temperature
Commercial
Industrial
DDR2 SDRAM component operating tempera-
ture2
Commercial
Industrial
Min
–0.5
–0.5
–20
–10
–5
–5
–8
0
–40
0
–40
Max
2.3
2.3
20
Units
V
V
µA
10
5
5 µA
8 µA
70 °C
85 °C
85 °C
95 °C
Notes:
1. The refresh rate is required to double when TC exceeds 85°C.
2. For further information, refer to technical note TN-00-08: "Thermal Applications," avail-
able on Micron’s Web site.
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN
8 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.







MT4HTF6464AY equivalent, schematic
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
Table 13: DDR2 IDD Specifications and Conditions (Die Revision E) – 512MB
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (32 Meg x 16) com-
ponent data sheet
Parameter
-80E/
Symbol -800 -667 -53E -40E Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC =
tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
IDD0
600 540 440 440 mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL =
4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
(IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data pattern is same as IDD4W
Precharge power-down current: All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
Active power-down current: All device banks open; tCK Fast PDN exit
= tCK (IDD); CKE is LOW; Other control and address bus in- MR[12] = 0
puts are stable; Data bus inputs are floating
Slow PDN ex-
it MR[12] = 1
Active standby current: All device banks open; tCK = tCK (IDD), tRAS =
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
700 520 480 460 mA
28 28 28 28 mA
300 260 180 160 mA
320 280 200 160 mA
160 120 120 120 mA
40 40 40 40
340 300 240 220 mA
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
IDD4W
IDD4R
IDD5
1260 800 720 640
1280 880 720 640
1120 1080 1000 960
mA
mA
mA
Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and IDD6 28 28 28 28 mA
address bus inputs are floating; Data bus inputs are floating
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2003 Micron Technology, Inc. All rights reserved.










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