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PDF ( 数据手册 , 数据表 ) MT36VDDT12872

零件编号 MT36VDDT12872
描述 1GB DDR SDRAM RDIMM
制造商 Micron
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MT36VDDT12872 数据手册, 描述, 功能
1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM
Features
DDR SDRAM RDIMM
MT36VDDT12872 – 1GB1
MT36VDDT25672 – 2GB1
MT36VDDT51272 – 4GB
For component data sheets, refer to Micron’s Web site: www.micron.com
Features
• 184-pin, registered dual in-line memory module
(RDIMM)
• Standard and low profile height PCB modules
• Fast data transfer rates: PC2100 or PC2700
• 1GB (128 Meg x 72), 2GB (256 Meg x 72),
and 4GB (512 Meg x 72)
• Supports ECC error detection and correction
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2-compatible)
• Internal, pipelined double data rate (DDR)
2n-prefetch architecture
• Bidirectional data strobe (DQS) transmitted/
received with data—that is, source-synchronous
data capture
• Differential clock inputs (CK and CK#)
• Multiple internal device banks for concurrent
operation
• Dual rank
• Selectable burst lengths (BL): 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes: 7.8125µs
maximum average periodic refresh interval
• Serial presence-detect (SPD) with EEPROM
• Selectable CAS latency (CL) for maximum
compatibility
• Gold edge contacts
184-Pin RDIMM Figures
Figure 1: Standard-Height Layout (MO-206)
PCB height: 43.18mm (1.7in)
Figure 2: Low-Profile Layout (MO-206)
PCB height: 30.48mm (1.2in)
Options
Marking
• Operating temperature2
Commercial (0°C TA +70°C)
Industrial (–40°C TA +85°C)
• Package
None
I
184-pin DIMM (standard)
G
184-pin DIMM (Pb-free)
• Memory clock, speed, CAS latency3
Y
6.0ns (167 MHz), 333 MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 24
7.5ns (133 MHz), 266 MT/s, CL = 24
-335
-262
-26A
7.5ns (133 MHz), 266 MT/s, CL = 2
-265
Notes: 1. End of life.
2. Contact Micron for industrial temperature
module offerings.
3. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
4. Not recommended for new designs.
PDF: 09005aef809d5451/Source: 09005aef807da325
dd36c128_256_512x72.fm - Rev. F 6/08 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.







MT36VDDT12872 pdf, 数据表
1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM
General Description
General Description
The MT36VDDT12872, MT36VDDT25672, and MT36VDDT51272 DDR SDRAM modules
are high-speed, CMOS dynamic random access 1GB, 2GB, and 4GB memory modules
organized in a x72 configuration. These modules use DDR SDRAM devices with four
internal banks.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for DDR SDRAM modules effectively consists of a single
2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM device
during READs and by the memory controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs(CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Control, command, and address signals are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Register and PLL Operation
These DDR SDRAM modules operate in registered mode, where the control, command,
and address input signals are latched in the registers on the rising clock edge and sent to
the DDR SDRAM devices on the following rising clock edge (data access is delayed by
one clock cycle). A phase-lock loop (PLL) on the module receives and redrives the differ-
ential clock signals (CK, CK#) to the DDR SDRAM devices. The register(s) and PLL reduce
control, command, address, and clock signals loading by isolating DRAM from the
system controller. PLL clock timing is defined by JEDEC specifications and ensured by
use of the JEDEC clock reference board. Registered mode will add one clock cycle to CL.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module
type and various DDR SDRAM organizations and timing parameters. The remaining 128
bytes of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0],
which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is connected
to VSS, permanently disabling hardware write protect.
PDF: 09005aef809d5451/Source: 09005aef807da325
dd36c128_256_512x72.fm - Rev. F 6/08 EN
8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved







MT36VDDT12872 equivalent, schematic
1GB, 2GB, 4GB (x72, ECC, DR) 184-Pin DDR RDIMM
Serial Presence-Detect
Serial Presence-Detect
Table 16: Serial Presence-Detect EEPROM DC Operating Conditions
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: IOUT = 3mA
Input leakage current: VIN = GND to VDD
Output leakage current: VOUT = GND to VDD
Standby current: SCL = SDA = VDD – 0.3V; All other inputs = VSS or VDD
Power supply current: SCL clock frequency = 100 kHz
Symbol
VDDSPD
VIH
VIL
VOL
ILI
ILO
ISB
ICC
Min
2.3
VDDSPD × 0.7
–1.0
Max
3.6
VDDSPD + 0.5
VDDSPD × 0.3
0.4
10
10
30
2.0
Units
V
V
V
V
µA
µA
µA
mA
Table 17: Serial Presence-Detect EEPROM AC Operating Conditions
Parameter/Condition
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA fall time
SDA rise time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Symbol
tAA
tBUF
tDH
tF
tR
tHD:DAT
tH:STA
tHIGH
tI
tLOW
fSCL
tSU:DAT
tSU:STA
tSU:STO
tWRC
Min
0.2
1.3
200
0
0.6
0.6
1.3
100
0.6
0.6
Max
0.9
300
300
50
400
10
Units
µs
µs
ns
ns
ns
µs
µs
µs
ns
µs
kHz
ns
µs
µs
ms
Notes
1
2
2
3
4
Notes:
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
Serial Presence-Detect Data
For the latest serial presence-detect data, refer to Micron’s SPD page:
www.micron.com/SPD.
PDF: 09005aef809d5451/Source: 09005aef807da325
dd36c128_256_512x72.fm - Rev. F 6/08 EN
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved










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